A precision CMOS analog cubing circuit

The practical implementation of a precision analog cubing function in 0.18 /spl mu/m CMOS technology is presented. The cubing circuit consumes less power, has a smaller layout area, and achieves a higher operating frequency than previously published designs. The circuit advantageously utilizes the non-square-law current-voltage characteristics of deep-submicron CMOS to achieve a precise cubing function. The effects of component mismatch on the output error are explored. A common-centroid layout is used to reduce component mismatch due to linear process, temperature, and stress gradients. The cubing circuit has a total DC current draw of 6.3 mA from a single 1.8 V supply. The maximum error between the simulated and ideal cubing response is /spl plusmn/0.7 mV over the output range /spl plusmn/30 mV for operating frequencies up to 1 GHz.