Frequency domain filter using an accurate reconfigurable FFT/IFFT core

As the time response for a given filter increases, frequency-domain implementation becomes attractive from a hardware resources point of view. This paper shows that for practical cases, the crossover between frequency-domain and time-domain implementations may be as low as 8 complex coefficients. The focus is on the design of efficient and reconfigurable FPGA implementations of frequency-domain filters. The filter size, binary word length of input, output, and coefficients are all configurable. Internal bus word lengths are also parameterized to control result accuracy. For example, a SQNR of 55 dB can be obtained for a 32 coefficient raised cosine filter of /spl alpha/=0.22 with 5 bit input and 12 bit output. This is compared to a maximum of 48 dB for a comparable FIR.