Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact

This letter reports the first full process integration of nanocrystal memory cell with 4.6 F/sup 2/ area ( NOR type), which is achieved by direct tungsten (W) bitline on self-aligned landing plug polysilicon contact. Prior to the nanocrystals (NCs) formation, surface hydroxylation of the tunnel SiO/sub 2/ by exposure to 1:99 hydrogen flouride (HF) is performed to maintain controllability of NCs. Also, the degradation of the tunnel SiO/sub 2/ caused by HF dipping is overcome to some extent through its fluorination. Robust four-threshold voltage (V/sub th/) states for 2-bit operation per cell are observed due to the localized injected charge and V/sub th/ asymmetry from different reading sensitivity to localized charges.