A novel memory controller for an ATM switch

The authors discuss some general approaches to ATM (asynchronous transfer mode) switching architectures, namely, common memory switches, Banyan networks, switch matrices, and bus-based time switches from a traffic behavior and implementation viewpoint. They focus on a novel controller hardware for the common memory type, which implements FIFO (first-in first-out) mechanisms as linked lists in hardware. The architecture for a 8*8 switch block implementation is elaborated in CMOS technology.<
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