Parasitic-aware synthesis of CMOS RF power amplifiers via simultaneous topology selection and device sizing

Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS 3.3 V three-stage 900 MHz power amplifier. Employing bond wire and spiral inductors, it achieves 30.8 dBm gain with 58.8% drain efficiency. The design was accomplished through simultaneous optimization of PA topology and device sizes using a new parasitic-aware RF circuit synthesis tool Arsyn. Combining local-search-enhanced genetic programming with effective design mining, Arsyn is orders of magnitude faster than traditional global optimization techniques such as simulated annealing and genetic searching while achieving the same solution quality.