High performance copper and low-k interconnect technology fully compatible to 90nm-node SOC application (CMOS4)

Dual damascene copper and low-k (k=2.9) interconnect technology for 90nm-node was successfully integrated. Structure and process are optimized to be compatible to transistor, memories, and packaging with consideration of RC delay and crosstalk between lines. Especially, aspect ratio of metal1 was carefully studied with electromigration durability data and DRAM pause time distribution data, because bit lines of embedded DRAM were formed with metal1. In order to demonstrate feasibility for manufacturing, six copper metal layers were fabricated on transistors and memories.