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SECTION I

WITH continued miniaturization of metal-oxide-semiconductor field-effect transistor (MOSFET) devices [1], [2], [3], [4], [5], [6], performance variability induced by process variability has become a critical issue in the design of VLSI circuits using advanced complementary metal-oxide-semiconductor (CMOS) technologies. Process variability has severely impacted delay and power variability in VLSI devices, circuits, and chips, and this impact keeps increasing as MOSFET devices and CMOS technologies continue to scale down [7], [8], [9], [10], [11]. The increasing amount of within-die process variability on the yield of VLSI circuits, such as static random access memory (SRAM), has imposed an enormous challenge in the conventional VLSI design methodologies. Similarly, the chip mean variation due to across the chip systematic process variability, also, imposes serious challenge in the conventional VLSI circuit design methodologies. Because of process variability constraints, an advanced VLSI circuit optimized using the conventional design methodology is more susceptible to random performance fluctuations. Thus, new circuit design techniques to account for the impact of process variability in VLSI circuits have become essential [7]. Although it is desirable to mitigate the risk of process variability on device and circuit performance by innovative device architectures [12], [13], process control, and a combination of process and circuit design techniques, modeling process variability is critical for variability-aware circuit design [7]. Thus, compact model addressing the impact of process variability in scaled MOSFET devices is crucial for computer-aided design (CAD) and analysis of advanced VLSI circuits.

In order to generate compact variability model for process variability-aware circuit design, a major set of model parameters sensitive to process variation is determined [7]. Typically, a standard set of model parameters is used to generate compact model library for worst-case analysis of circuit performance [7]. However, for realistic process variability modeling, a large sample of production control electrical test (ET) data is collected from different wafers and wafer-lots over a period of time [14], [15], [16]. Then a set of process variability-sensitive model parameters is determined by principle component analysis (PCA) [14]. Though PCA is the most effective way to determine the process variability-sensitive device parameters, it is resource intensive and not suitable for concurrent next generation technology and product development. Similarly, a standard set of model parameters is inadequate for characterizing process variability in nanoscale MOSFET devices. Therefore, it is crucial to adopt an analytical approach to determine the process variability-sensitive critical model parameters for compact variability modeling. In this paper, we present a generalized methodology to determine the device parameters most sensitive to process variation and map each of these device parameters to the corresponding compact model parameters to build compact model library for variability-aware VLSI circuit analysis.

The objective of this paper is to present a systematic methodology to develop compact MOSFET model library for variability-aware VLSI circuit design. In order to achieve this goal, first of all, the paper reviews the critical sources of process variability in scaled MOSFET devices along with their impact on advanced VLSI device performance. Then a brief overview of different approaches to modeling process variability for VLSI circuit CAD is described. After reviewing the conventional process variability modeling approaches, the paper presents an analytical approach to generate compact model library for variability-aware circuit design. In this approach, first the major set of MOSFET device parameters sensitive to the local and global process variability is determined from the basic device theory. Then each process variability-sensitive device parameter is mapped to the corresponding compact model parameter of the target compact model (e.g., BSIM4 [17]). After parameter mapping, a simplified procedure is used to generate compact MOSFET model library for variability-aware VLSI circuit optimization.

SECTION II

Generally, the intrinsic sources of variability in VLSI device performance arise from random variability of wafer fabrication processing steps [7], [9]. Typically, the intrinsic process variability is grouped as stochastic and systematic. The stochastic group is defined as the local or intra-die process variability and the systematic component is defined as the global or inter-die process variability [7], [8], [9], [10], [11]. Local process variability causes parametric fluctuations or mismatch between identically designed devices within a die, whereas the global process variability causes die-to-die, wafer-to-wafer, or lot-to-lot systematic parametric fluctuations between identical devices [7], [8], [9], [10]. Global variability causes a shift in the mean value of the sensitive design parameters, including the channel length $(L)$, channel width $(W)$, gate oxide thickness $(T_{ox})$, resistivity, doping concentration, and body effect [7]. The major sources of intrinsic process variability in advanced CMOS technologies include random discrete doping (RDD), line-edge roughness (LER), line-width roughness (LWR), and oxide thickness variation (OTV) as shown in Fig. 1 [7], [8], [9], [10].

The detailed description of the major sources of front-end process variability in metal-oxide-semiconductor (MOS) devices and their impact on device performance is reported in [7] and is summarized in subsections $A$–$D$ below:

In the channel region of an MOS device, RDD results from the discreteness of dopant atoms as shown in Fig. 1. In an MOS device, the channel region is doped with dopant atoms to control its threshold voltage $(V_{th})$. For a device with channel doping concentration $N_{CH}$, and source/drain (S/D) junction depth $X_{j}$, the total number of dopant atoms in the channel region is given by [7]: TeX Source $$N_{CHtotal}\cong N_{CH}(W.L.X_{j})\eqno{\hbox{(1)}}$$

Equation (1)shows that the continuous scaling down of $L$, $W$, and $X_{j}$ causes $N_{CHtotal}$ to decrease, despite the corresponding increase in the channel-doping concentration according to CMOS scaling guidelines [1], [2], [3]. Using (1) and data for advanced CMOS technology scaling from ‘’ [18], the estimated decrease in $N_{CHtotal}$ over the scaled technology nodes is shown in Fig. 2. Fig. 2 implies that the number of dopants in a transistor channel is a discrete statistical quantity with probability to occupy any random location. Therefore, in an advanced CMOS technology, two identical transistors sitting side by side have different electrical characteristics because of the randomness in a few dopant atoms, resulting in intra-die device and circuit performance variability.

The major effects of RDD are significant variability in MOSFET threshold voltage $V_{th}$, variability in the overlap capacitance due to uncertainty in the position of S/D dopants under the gate, and variability in the effective S/D series resistance $(R_{DS})$. The impact of RDD-induced process variability on $V_{th}$ mismatch between two identically designed within-die devices is given by [19], [20]: TeX Source $$\sigma V_{th,RDD}\cong C.\left(\root{4}\of{{q^{3}\varepsilon_{Si}\phi_{B}}}\right){{T_{ox}}\over{\varepsilon_{ox}}}\left(\root{4}\of{{N_{CH}}}\over{\sqrt{W_{eff}L_{eff}}}\right)\eqno{\hbox{(2)}}$$ where $C$ is a number and is given by 0.8165 [19]or 0.7071 [20] with or without the dopant variation along the depth of the channel region, respectively; $q$ is the electronic charge, $\varepsilon_{Si}$ and $\varepsilon_{ox}$ are the permittivity of silicon and silicon-dioxide $({\rm SiO}_{2})$, respectively; $\phi_{B}=2k_{B}T\ln (N_{CH}/n_{i})$ is the bulk potential of the channel region of MOSFETs with $k_{B}$, $T$, and $n_{i}$ are the Boltzmann constant, absolute temperature, and intrinsic carrier concentration, respectively; and $W_{eff}$ and $L_{eff}$ represent the effective dimension of $W$ and $L$, respectively. Since the device area $(W_{eff}L_{eff})$ decreases with each new technology generation, the net result of RDD is a significant increase in process variability for scaled CMOS technology as shown in Fig. 3. In fact, RDD is a major contributor to the mismatch $(\sigma V_{th})$ in advanced MOSFETs [21]. As the device size scales down, $N_{CHtotal}$ decreases as shown in Fig. 2, resulting in a larger variation of dopant numbers, and significantly impacting $V_{th}$ as shown in Fig. 3.

In CMOS technology, LER results from sub-wavelength lithography and etching process that causes variation in the critical dimension (CD) of the transistor feature size as shown inFig. 1 [22]. The impact of LER includes variation in $V_{th}$ and higher subthreshold current. LER-induced $V_{th}$ mismatch depends on the variability in $W_{eff}$ of MOSFETs and is given by [7], [22], and [23]: TeX Source $$\sigma V_{th,LER}\propto{{1}\over{\sqrt{W_{eff}}}}<\sigma V_{th,RDD}\eqno{\hbox{(3)}}$$

Thus, LER increases as VLSI technology scales down. In scaled MOSFET devices, LER has become a larger fraction of $L$ and a major source of intrinsic statistical variation causing significant variability in VLSI device and circuit performance. The mismatch due to LER and RDD is statistically independent and can be modeled independently [7].

In CMOS technologies, OTV is caused by atomic level interface roughness between silicon and gate dielectric and remote interface roughness between gate material and gate dielectric, hereafter referred to as the “surface roughness (SR),” as shown in Fig. 1. This SR causes fluctuations of the voltage drop across the oxide layer resulting in $V_{th}$ variation [7], [24], [25]. In nanoscale MOSFETs, OTV is becoming more dominant as $T_{ox}$ approaches to the length of a few silicon atoms and is comparable to the thickness of interface roughness.

In nano-MOSFET devices, OTV causes significant device parameter variability. In polysilicon gate MOSFETs, OTV introduces a gate current $(I_{\rm g})$ variation. This $I_{\rm g}$ variation induces a voltage drop in the polysilicon gate and significantly changes $V_{th}$. In addition, the device transconductance, $g_{m}$ changes significantly because of the reduction in the gate voltage $V_{gs}$ due to the voltage drop in the polysilicon gate. In high-$k$ gate dielectric and metal gate devices, OTV introduces significant mobility degradation [7].

Other sources of process variability include variation associated with polysilicon as well as metal gate granularity [26], [27]; variation in fixed charge [28], and defects and traps in gate dielectric [29]; variation associated with patterning proximity effects such as optical proximity correction [30]; variation associated with polish such as shallow-trench isolation [31] and gate [32]; variation associated with the strain such as in wafer-level biaxial strain [33], high-stress capping layers [34], and embedded silicon germanium (SiGe) [35]; and variation associated with implants and anneals due to implant tools, implant profiles, and millisecond annealing [36], [37].

Thus, from the above discussions, it is clear that the advanced CMOS process technologies introduce within-die random performance variability which causes severe variability in the performance of advanced VLSI circuits and systems. Therefore, it is critical to accurately model process variability when predicting the performance of advanced VLSI circuits and systems.

SECTION III

In order to account for process variability in circuit performance, typically, corner models are used to set the lower and upper limits of process variation. These models are implemented in the process-design kit (PDK) to support process variability-aware VLSI circuit design.

In conventional circuit design technique, process variability is modeled by four worst-case corners—two for analog applications and two for digital [7]. The corner models for analog applications are generated from slow nMOS and slow pMOS (SS) to model the worst-case speed (WS), and from fast nMOS and fast pMOS (FF) to model the worst-case power (WP); whereas, the corner models for digital applications are generated from fast nMOS and slow pMOS (FS) to model the worst-case ‘1,’ (WO) and from slow nMOS and fast pMOS (SF) to model the worst-case ‘0’ (WZ). A standard set of model parameters (e.g., $V_{th})$ is used to account for process variability and model the worst-case corner performance of devices and circuits of the target CMOS technology [7].

In this modeling approach, the standard deviation $(\sigma)$ limits are preset pessimistically to include any potential process variability over a wide range. The worst-case corner models are generated by offsetting the selected compact-model parameters, $P$ of the typical (TT) compact model by $\pm\,dP=n\sigma$ to account for the window of process variability, where $n$ is the number of $\sigma$ for $P$ so that $3\leq n\leq 6$ is selected to set the fixed lower and upper limits, LL and UL, respectively of the worst-case models; and TT is the typical compact model extracted from the “golden die” of the “golden wafer” representing the centerline process technology [7]. For example, the corner models of a BSIM4 TT model parameter $V_{\rm TH0}$ is defined as $V_{\rm TH}=V_{\rm TH0}\pm dvth$ where dvth is used to set the fixed LL and UL of the worst-case models.

In order to obtain the worst-case corner of drain current $I_{ds}$, we consider the basic $I_{ds}$ expression in the ON state of large MOSFETs [38]: TeX Source $$I_{ds}\cong\left({{W}\over{2L}}\right)\mu_{eff}C_{ox}\left({V_{gs}-V_{th}}\right)^{2}; 0\!<\!\left({V_{gs}\!-\! V_{th}}\right)\geq V_{ds}\eqno{\hbox{(4)}}$$ where $\mu_{eff}$, $C_{ox}$, and $V_{ds}$ are the inversion carrier mobility, gate oxide capacitance, and drain to source voltage, respectively; and the remaining parameters have their usual meanings as defined earlier. Then, the UL is set by taking the appropriate maximum or minimum offset of the device parameters to maximize the value of $I_{ds}$. Thus, the UL of ION for nMOSFETs is given by: TeX Source $$\eqalignno{&IONN(UL)\cong\mu_{eff}\left({{W+dW}\over{2(L-dL)}}\right)\left({{\varepsilon_{ox}}\over{T_{ox}-dT_{ox}}}\right)\cr&\qquad\qquad\qquad\times\left({V_{gs}-\left({V_{th}-dV_{th}}\right)}\right)^{2}&{\hbox{(5)}}}$$

In (5), $W$ is increased by dW, $L$ is reduced by dL, $T_{ox}$ is reduced by $dT_{ox}$, and $V_{th}$ is reduced by $dV_{th}$ to achieve the UL of $I_{ds}$ specification. Similarly, the LL for ION is set by: TeX Source $$\eqalignno{&IONN(LL)\cong\mu_{eff}\left({{W-dW}\over{2(L+dL)}}\right)\left({{\varepsilon_{ox}}\over{T_{ox}+dT_{ox}}}\right)\cr&\qquad\qquad\qquad\times\left({V_{gs}-\left({V_{th}+dV_{th}}\right)}\right)^{2}&{\hbox{(6)}}}$$

Fig. 4 shows ION-plots for both n/pMOSFETs obtained by fixed-corner models along with the distribution of ET data. It is observed from Fig. 4 that the simulation results obtained by fixed-corner models are too wide, so it could end up rejecting a valid design, causing yield loss. The major problems with the worst-case corner models are that in most cases the existing correlations between the device parameters are ignored and the models include pessimistic corner values. As a result, the models generate a large spread of data during circuit simulation [7].

The worst-case corner models offer designers capability to simulate the pass/fail results of a typical design and are usually pessimistic.

Unlike fixed corner models, the statistical corner models are generated using ET data from different die, wafers, and wafer lots collected over a certain period of time to represent realistic process variability of a target technology [14], [15], [16]. Some of the methodologies used to generate statistical corner models are briefly outlined below:

In one approach, ET data are measured from a large number of sites of the target technology. And, for each site of ET data a compact model file is generated. Thus, a large number of compact model files, referred to as the “performance aware model (PAM)” cards are generated for any target technology [39], [40]. In this approach about 1000 PAM cards or model files are generated for realistic statistical analysis of circuit performance.

In this modeling approach, ET data are used to determine the depth of the location of device parameters in the distribution for corner model generation, referred to as the “location depth corner modeling (LDCM)” [41]. In LDCM, the wafers corresponding to the extreme data points in the distribution are used to extract separate compact models. Thus, using LDCM, the number of model cards $({<}{20})$ is significantly reduced in contrast to PAM. An enhanced LDCM (ELDCM) is used with proper guard banding to ensure design validation against future process shift from the baseline specifications [41].

The statistical modeling approach, referred to as the “backward propagation of variance (BPV) [42],” formulates statistical models as a set of independent, normally distributed process parameters $P$. These parameters control the variations seen in the device electrical performances through the behavior described in the TT compact models. With recent extensions [43], BPV is used to characterize physical process related compact model parameters. For accurate analysis of process variability induced circuit performance variability using BPV, the TT model file must be physical, the sensitivity matrix must be well-conditioned, and the variances of parameters must be physically consistent.

Thus, in the conventional variability modeling approaches, a standard set of model parameters are used for fixed corner modeling or a large number of model files are generated from ET data. The fixed corner models are inadequate whereas, ET-data based modeling is resource-intensive. Therefore, an analytical technique to obtain the process-sensitive compact model parameters of any compact model to generate compact variability model for circuit analysis is crucial for variability-aware circuit design as described in Section IV.

SECTION IV

A generalized approach for process variability modeling is shown in Fig. 5. The method includes selection of target compact model; consideration of basic $I_{ds}$ expression; derivation of a generalized expression of $I_{ds}$ variance; selection of device parameters causing process-induced $I_{ds}$ variation; mapping process-sensitive device parameters to corresponding compact model parameters; determination of variances for mismatch modeling and global variability modeling; and finally, build compact variability model.

The modeling methodology outlined in Fig. 5 is described in the Section V.

It is clear from our discussions in Section II that process variability causes variability in MOSFET device performance which in turn causes variability in VLSI circuit performance. Since, the MOSFET device performance is determined by $I_{ds}$, therefore, in order to determine the impact of process variability on circuit performance, we determine the process variability-sensitive device parameters causing $I_{ds}$ variability. For the selection of major process variability-sensitive device parameters, we consider the basic $I_{ds}$ model in the sub-threshold, linear, and saturation region of MOSFETs [38]: TeX Source $$I_{ds}\cong\cases{\left({{W}\over{L}}\right)\mu_{eff}\eta e^{{V_{gs}-V_{th}}\over{nkT}}\left({1-e^{-{{V_{ds}}\over{kT}}}}\right);\cr\hskip12.5em\left({V_{gs}-V_{th}}\right)\leq 0\cr\left({{W}\over{L}}\right)\mu_{eff}C_{ox}\left({V_{gs}-V_{th}-{{V_{ds}}\over{2}}}\right)V_{ds};\cr\hskip9.5em0<\left({V_{gs}-V_{th}}\right)\leq V_{ds}\cr\left({{W}\over{2L}}\right)\mu_{eff}C_{ox}\left({V_{gs}-V_{th}}\right)^{2};\cr\hskip9.5em0<\left({V_{gs}-V_{th}}\right)\geq V_{ds}\cr}\eqno{\hbox{(7)}}$$ where $\eta$ is a constant and depends on the channel depletion capacitance $(C_{d})$ and ambient temperature, $T$; $n$ is the ideality factor of sub-threshold slope and depends on $C_{ox}$ and ${\rm C}_{d}$; and, the remaining parameters have their usual meanings as defined earlier. From (7), we determine the major device parameters most sensitive to process variability in each region of MOSFET device operation.

The local process variability or mismatch between identically designed transistors is caused by microscopic process that makes every transistor different from its neighbors [8], [9], [10], [11], [12]. As a result, a device parameter $P$ can be considered as consisting of a fixed component $P_{0}$ and a randomly varying component $p$ resulting in different values of $P$ for closely apart identical paired-transistors. Then the difference $\Delta P$ between two identical transistors within a die is a randomly varying parameter and is defined as the ‘mismatch’ in $P$ between two identical-paired transistors. For a large number of samples, $\Delta P$ converges to a Gaussian distribution with zero mean. Then the mismatch in relative drain current, $\Delta I_{ds}/I_{ds}$ between paired-transistors due to $P$ is given by [46]: TeX Source $$\eqalignno{&\sigma_{\Delta I_{ds}/I_{ds}}^{2}=\sum_{i=1}^{l}{\left({{{1}\over{I_{ds}}}{{\partial I_{ds}}\over{\partial P_{i}}}}\right)^{2}\sigma_{\Delta P_{i}}^{2}}\cr&\qquad\qquad\quad+{{2}\over{I_{ds}^{2}}}\sum_{i=1}^{l}{{{\partial I_{ds}}\over{\partial P_{i}}}{{\partial I_{ds}}\over{\partial P_{i+1}}}\rho\left({\Delta P_{i},\Delta P_{i+1}}\right)}&{\hbox{(8)}}}$$ where $l$ is the total count of $\Delta P$ contributing to $I_{ds}$ mismatch; $\Delta P_{i}$ is the $i$th count of $\Delta P$ with standard deviation $\sigma_{\Delta P_{i}}$; and $\rho\left({\Delta P_{i},\Delta P_{i+1}}\right)$ is the correlation between $\Delta P_{i}$ and $\Delta P_{i+1}$. Since $\Delta P_{i}$ is random and independent, therefore, the correlation $\rho\left({\Delta P_{i},\Delta P_{i+1}}\right)=0$. In order to model $I_{ds}$ mismatch between paired-transistors, we determine the major local process variability-sensitive device parameters $P$.

From (7), we find that for all regions of MOSFET device operation, the value of $I_{ds}$ depends on a common set of parameters $\left\{{V_{th},W,L,C_{ox},\mu_{eff},V_{gs},V_{ds}}\right\}$. We know, $C_{ox}={\rm f}(T_{ox})$, then considering only parametric variation, in (8), $\Delta P$ represents any of the mismatch parameters of the set $\left\{{\Delta V_{th},\Delta W,\Delta L,\Delta T_{ox},\Delta\mu_{eff}}\right\}$. It is to be noted that the parameter set $\left\{{\Delta W,\Delta L,\Delta T_{ox},\Delta\mu_{eff}}\right\}$ describes the current gain $\beta=\left({(W/L)C_{ox}\mu_{eff}}\right)$ mismatch. Again, $V_{th}$ can be expressed as $V_{th}={\rm f}\left({V_{th0},\gamma,\phi_{S},V_{bs}}\right)$, where $V_{bs}$ is the applied body bias and $V_{th0}=V_{th}$ at $V_{bs}=0$ whereas, $\gamma$ and $\phi_{S}$ are the body effect coefficient and channel surface potential, respectively. Here, $\Delta V_{th0}$ describes the mismatch $\Delta I_{ds}(V_{bs}=0)$ due to RDD of the channel doping concentration $N_{CH}$ of MOSFETs whereas, $\Delta\gamma$ describes the mismatch in $\Delta I_{ds}(V_{bs})$ due to the variation in $N_{CH}$ in the depletion region under the gate. We know that $\gamma={\rm f}(N_{CH},V_{bs})$ and with the change in the value of $V_{bs}$, the width of the depletion layer under the gate changes [19]. As a result, the amount of bulk charge, $qN_{CH}$ changes with the changes in $V_{bs}$ as shown inFig. 6 for the graded-retrograde channel doping profile [12]. Thus, RDD of the vertical channel doping profile under the gate contributes to the mismatch in $I_{ds}(V_{bs})$. Hence, $I_{ds}(V_{bs})$ mismatch between the identical paired-transistors due to variation in the vertical channel doping concentration must be modeled by $\gamma$.

Thus, the set of major local process variability-sensitive device parameters contributing to the mismatch between identically designed paired-transistors within a die is $\left\{V_{th0},W,L,T_{ox},\mu_{eff},\gamma\right\}$ as shown in Table I. Here, $\Delta V_{th0}$ describes the variation in $\Delta I_{ds}$ due to RDD; $\Delta W$ and $\Delta L$ describes $\Delta I_{ds}$ due to LER and LWR; $\Delta T_{ox}$ defines $\Delta I_{ds}$ due to OTV; $\Delta\mu_{eff}$ defines $\Delta I_{ds}$ due to mobility variation caused by SR scattering; and $\gamma$ models $\Delta I_{ds}(V_{bs})$ due to RDD in the vertical channel doping profile. Therefore, we have used the basic $I-V$ relation to determine the major process variability-sensitive device parameters for modeling mismatch in VLSI circuits.

The global process variability is caused by non-uniform processing temperature as well as the variation of implant doses across wafers and relative location of devices [7], [8]. The global variation shifts the average or mean value of device performance. As a result, a device parameter within a chip varies for two identically designed devices. For a large count of $P$ from a large number of on-chip measurement data, $P$ converges to a Gaussian distribution with mean value $P_{0}$ and standard deviation $\sigma=\Delta P$. Then the chip mean variation in $I_{ds}$ due to global process variability-sensitive parameter $P$ is given by: TeX Source $$\sigma_{I_{ds}}^{2}=\sum_{i=1}^{l}{\left({{\partial I_{ds}}\over{\partial P_{i}}}\right)^{2}\sigma_{P_{i}}^{2}+2\sum_{i=1}^{l}{{{\partial I_{ds}}\over{\partial P_{i}}}{{\partial I_{ds}}\over{\partial P_{i+1}}}}}\rho\left({P_{i},P_{i+1}}\right)\eqno{\hbox{(9)}}$$ where $l$ is the total number of occurrence of the device parameters $P$ contributing to global $I_{ds}$ variation; $P_{i}$ is the $i$th count of $P$ with standard deviation $\sigma P_{i}$ from its mean value $P_{0}$; and $\rho\left({P_{i},P_{i+1}}\right)$ is the correlation between the occurrence $P_{i}$ and $P_{i+1}$. In order to model the variation of $I_{ds}$ around its mean value, we determine the major global process variability-sensitive parameters $P$.

Again, from (7), the chip mean variation of $I_{ds}$ due to global process variability can be described by the parameter set $\left\{V_{th0},W,L,C_{ox},\mu_{eff},\gamma\right\}$. In addition, the $I_{ds}$ variability due to the variation in the S/D ion implantation dose and processing temperature across wafers are described by the variation in the S/D series resistance, $R_{DS}$ of MOSFET devices. Furthermore, the gate delay, $\tau_{pd}\propto C_{load}$, where $C_{load}$ is the load capacitance of the inverter circuit. Therefore, for an accurate simulation of digital circuits, the across the chip variation in MOSFET gate capacitance $(C_{g})$ along with the S/D junction capacitance $(C_{J})$ must be modeled. Now, the variability in the mean value of $C_{g}$ is described by the gate overlap capacitance $(C_{ov})$ whereas, that in $C_{J}$ is described by the S/D area as well as S/D side-wall and isolation-edge sidewall capacitances. Thus, the variation in the ac and transient performance of VLSI digital circuits are, also, described by an additional parameter set $\left\{{C_{ov},C_{J}}\right\}$. Therefore, the set of major MOSFET device parameters sensitive to global process variability can be represented by $\left\{V_{th0},W,L,T_{ox},\mu_{eff},\gamma,R_{DS},C_{ov},C_{j}\right\}$ as shown in Table II.

In order to develop compact MOSFET model to analyze the impact of process variability in advanced VLSI circuits, the process variability-sensitive device parameters $P$ selected in Section IV-A are mapped to the corresponding compact model parameter $\{M\}$ of the selected compact model. In this study, we select BSIM4 compact model to show the methodology of generating compact MOSFET variability model library for VLSI circuit CAD.

In Section IV-A-I, we have presented an analytical approach to select the randomly variable set of device parameters, $\{V_{th0},W,L,T_{ox},\mu_{eff},\gamma\}$, causing mismatch between identically designed paired-transistors. The corresponding set of BSIM4 MOS model parameters, shown in Table I, is $\left\{V_{TH0},XW,XL,TOX,U0,K1\right\};$ where, $XW$ and $XL$ are the channel width and length offset parameters due to masking and photolithography, respectively and account for the mismatch due to LER and LWR; whereas, $U0$ and $K1$ account for the variation in $\mu_{eff}$ and $N_{CH}$ under $V_{bs}$, respectively. In order to build the compact model, the variance $\sigma_{\Delta M_{mismatch}}$ for each $M$ is determined from a large set of data to account for the mismatch in identical paired-transistors.

In Section IV-A-II, we have shown an analytical approach to determine the critical set of device parameters, $\left\{V_{th0},W,L,T_{ox},\mu_{eff},\gamma,R_{DS},C_{ov},C_{j}\right\}$, impacting MOSFET device performance due to global process variability. The corresponding set of BSIM4 compact model parameters is $\{{\rm VTH0},{\rm XW},{\rm XL},{\rm TOX},{\rm U0},{\rm K1},{\rm RDSW},{\rm CGSO},{\rm CGDO},{\rm CGSL},{\rm CGDL},{\rm CJS},{\rm CJD},{\rm CJSWS},{\rm CJSWD},{\rm CJSWGS},{\rm CJSWGD}\}$; where the parameter set $\{{\rm CGSO},{\rm CGDO},{\rm CGSL},{\rm CGDL}\}$ defines ${\rm C}_{ov}$; $\{{\rm CJS},{\rm CJD}\}$ defines S/D junction area capacitance; and $\{{\rm CJSWS},{\rm CJSWD},{\rm CJSWGS},{\rm CJSWGD}\}$ defines S/D junction sidewall capacitance as shown in Table II. For each $M$, the variance $\sigma M_{global}$ is obtained from a large set of ET data and added to the mean value, $M_{0}$ to analyze the impact of chip mean variation on VLSI circuits.

The variance $\sigma M$ of the compact model parameter $M$ due to process variability is included to the mean (TT) value $M_{0}$ to model the impact of process variability on VLSI circuit performance.

For a large number of samples $\Delta M_{mismatch}$ between paired-transistors is described by standard normal distribution, $N\left({0,\sigma_{\Delta M_{mismatch}}}\right)$ where the variance $\sigma_{\Delta M_{mismatch}}$ is given by: $\left.{\sigma_{\Delta M_{mismatch}}}\right\vert_{pair}\cong A_{M}/\sqrt{WL}$ [47], [48]; here the parameter $A_{M}$ is a technology dependent constant of $\Delta M$ and is extracted from $\Delta M_{i}$ versus $\left(\!{1/\sqrt{WL}}\!\right)$ plot for a large number $(i=1, 2, 3,\cdots l)$ of sample ET data [8], [47], [49]. Thus, for the compact model parameter ${\rm V}_{TH0}$, the variance of $\Delta V_{TH0}$ between two paired-transistors is given by: TeX Source $$\left.{\sigma_{\Delta VTH{0}}}\right\vert_{pair}\cong{{A_{vt}}\over{\sqrt{WL}}}\eqno{\hbox{(10)}}$$ where $A_{vt}$ is the area dependent constant of $\Delta V_{TH0}$. Typically, mismatch $\Delta VTH 0$, $\Delta XW$, $\Delta XL$, $\Delta T_{ox}$, $\Delta U0$, and $\Delta K1$ are represented by (8). Again, since $\Delta M_{i}$ is random and independent, therefore, the correlation $\rho\left(\Delta M_{i},\Delta M_{i+1}\right)=0$ [49]. Then, for a single device we get: TeX Source $$\sigma M_{mismatch}={{1}\over{\sqrt 2}}\sigma_{\Delta M_{i}}={{1}\over{\sqrt 2}}{{A_{M}}\over{\sqrt{WL}}}.\eqno{\hbox{(11)}}$$

In (11), $\sigma M_{mismatch}$ represents the variance of $\Delta M$ due to within-die stochastic process variability. Thus, the variance of $\Delta V_{TH0}$ is given by: TeX Source $$\sigma V_{TH0,mismatch}={{1}\over{\sqrt 2}}\sigma_{\Delta V_{TH0}}={{1}\over{\sqrt 2}}{{A_{vt}}\over{\sqrt{WL}}}\eqno{\hbox{(12)}}$$

For statistical compact modeling, $\sigma M_{mismatch}$ for each variability-sensitive model parameter is added to the corresponding $M_{0}$ to compute the mismatch between paired-transistors. Typically, for each $M$, $A_{M}$ is extracted from Pelgrom's plot from a large set of measurement data [47], [48]. For next generation technology development, a large set of data is obtained by calibrated numerical process and device CAD to compute $\sigma M_{mismatch}$ for each variability-sensitive compact model parameters [50], [51], [52], [53], [54].

For MC statistical modeling, $M_{global}$ is described by normal distribution $N(M_{0},\sigma M_{global})$, around its mean (TT) value $M_{0}$. The global variance $\sigma M_{global}$ is obtained from the statistical distribution of ET data for each $M$ measured from multiple die, wafers, and lots over a period of time [7]. However, for the next generation technology development, ET data are scarcely available for statistical analysis. In this case, the numerical simulation data can be used for the computation of $\sigma M_{global}$ and generate rev0 compact model for circuit analysis of the target technology [50], [51], [52], [53], [54]. Typically, $n\sigma M_{global}$ is used to model global process variability with $3\leq n\leq 6$.

As described in Section III-A, the TT model for circuit CAD consists of a set of parameters $\{M_{0}\}$ that models the device and circuit performance of centerline process of the target technology node. The set $\left\{{M_{0}}\right\}$ represents the nominal device specifications of the target technology. The local and global components of the variability-sensitive compact model parameter are included in the nominal set $\left\{{M_{0}}\right\}$ to generate compact variability model for circuit CAD. The final model includes the nominal parameters with the components of process variability. Thus, a process variability-sensitive model parameter $M$ including both local and global process variability components is given by: TeX Source $$M=M_{0}+\sigma M_{mismatch}+n\sigma M_{global}\eqno{\hbox{(13)}}$$

Equation (13) is used to build the compact model of the target technology for process variability-aware circuit analysis. Thus, for the compact model parameter $V_{TH}$, (13) yields: TeX Source $$V_{TH}=V_{TH0}+\sigma V_{TH0,mismatch}+n\sigma V_{TH0,global}.\eqno{\hbox{(14)}}$$

Equation (13) is used to build statistical corner model for realistic analysis of process variability in scaled MOSFETs. Table III shows FF and SS corner limit of the set of process variability-sensitive model parameters obtained by analytical approach discussed in Section IV-B.

For Monte Carlo (MC) statistical compact modeling, the probability distribution function (PDF) of the mismatch component of $M$ for HSPICE circuit CAD is obtained by [55]: TeX Source $$PDF(\sigma M_{mismatch})=(\sigma M_{mismatch})agauss(0,1,1)\eqno{\hbox{(15)}}$$ Similarly, the PDF for the global component of $M$ is expressed as: TeX Source $$PDF(\sigma_{global})=(\sigma_{global})agauss(0,1,3)\eqno{\hbox{(16)}}$$

Equation (15) and (16) are used in (13) to formulate the variability-sensitive compact model parameters to develop the final model library for HSPICE circuit CAD. Table IV shows the formulation of variability-sensitive BSIM4 model parameters in the model library. Thus, for the variability-sensitive $V_{TH}$, we have: TeX Source $$\eqalignno{&V_{TH}=V_{TH0}+{{1}\over{\sqrt 2}}{{Avt}\over{\sqrt{WL}}}agauss(0,1,1)\cr&\quad\qquad+\,\sigma V_{TH0}agauss(0,1,3)&{\hbox{(17)}}}$$

The above procedure is used to build BSIM4 MOSFET compact model library for the advanced CMOS technology reported in [3], [4], [5]. For the simplicity of showing the basic functionality of the present modeling approach, all mismatches are lumped into $V_{th}$ mismatch and the correlation between the model parameters is ignored.

SECTION V

The model library developed in Section IV is used for MC statistical analysis of advanced MOSFET devices [3], [4], [5]. Fig. 7 shows the distribution of IONN and IONP obtained by HSPICE circuit simulation [55]. Here, ION is defined at $\vert V_{gs}\vert=\vert V_{ds}\vert=1~{\rm V}$ for 20 nm technology [5], [6]. The IONN versus IONP distribution in Fig. 7, clearly, shows the impact of local process variability or mismatch, global process variability or chip mean variation, and the local and global process variability combined. In Fig. 7, the simulation data from statistical corner values of IONN and IONP are, also superimposed on the plot for reference. In Fig. 7, FF and SS corner encloses the MC distribution of ON currents. Thus, in contrast to fixed pessimistic corners, shown in Fig. 4, the statistical corners offer realistic analysis of process variability similar to MC analysis as shown in Fig. 7. Fig. 7, also, shows that local variability is a significant factor of the total $({\rm global}+{\rm local})$ variability as observed for advanced technologies [56]. Thus, it is critical to accurately model local fluctuations in advanced CMOS technologies.

SECTION VI

This paper presented a systematic procedure to determine process variability-sensitive compact model parameters and develop statistical compact models to investigate the impact of process variability on circuit performance. The present analytical approach to determine variability-sensitive compact model parameters is cost-effective and efficient compared to the time consuming and expensive PCA and ET data-based approaches for statistical compact modeling. The proposed method, also, allows generating realistic statistical corners compared to pessimistic fixed corners and can be used to generate statistical compact models from the basic expressions for device performance using numerical simulation data. This statistical corner models enable designers to assess the impact of process variability on circuit performance without time consuming MC analysis. The proposed approach is ideal for developing statistical compact model of next generation technology where data for statistical analysis are not available. The future consideration of this procedure is to include correlation factors among the process variability-sensitive global model parameters. And, include adequate process variability-sensitive sub-threshold region compact model parameters to analyze the impact of process variability on sub-threshold performance of analog circuits. The present statistical-modeling approach enables realistic assessment of the standard deviation of circuit performance and allows for tracking circuit performance due to process variability. In addition, the present methodology offers concurrent next generation technology and product development. Though the present methodology is used to generate statistical compact models using BSIM4, it can be applied to any compact models considering the basic equations for device performance.

Grateful thanks are due to Mr. Balasubramanian Murugan for valuable comments and suggestions during this work.

S. K. Saha is with the Prospicient Devices, Milpitas, CA 95035, USA (e-mail: samar@ieee.org)

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

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