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  • Abstract



HIGH precision TDCs are widely used in particle physics and plasma experiments in space, such as in the CLUSTER mission launched in 2000 [1], the ROSETTA mission launched in 2004 [2], the PAMELA mission launched in 2006 [3], [4], and in the AMS-02 mission launched in 2011 [5], [6].

Among these applications, implementing the TDC in a FPGA chip is an attractive solution due to its good flexibility and low cost. The PAMELA mission [4] employs TDCs that are implemented in Actel FPGAs to provide time-of-flight (TOF) particle identification. Using the time stretch method, the TDC achieves a resolution of 10 ns and a time range of 40.95 us, which means a 50 ps resolution and a 200 ns dynamic range with an expansion factor of 200. The TOF system of ESA ROSETTA mission [2], which employs TDCs implemented in Actel radiation-tolerant FPGAs, can achieve a resolution of 2 ns, 256 us dynamic range using the “tapped delay line” method, and have a short dead time of 10 ns.

J. Song studied a high resolution TDC approach, suggesting a time interpolating method that employs dedicated carry lines as the delay elements in SRAM FPGAs [7]. According to the studies of J. Wang, a 50 ps resolution and a 10 ns dead time can be achieved using dedicated carry lines for time interpolation [8]. However, when the SRAM FPGAs are used in space missions, Triple Module Redundancy (TMR), Error Correcting Code (ECC), Error Detection (ED), Reconfiguration or other methods are needed for Single-Event-Upset (SEU) mitigation. Thus more FPGA resources will be occupied, and the TDC structure becomes more complicated. On the other hand, both Actel flash-based and anti-fuse FPGAs show good performance with regard to SEU and Single-Event-Latchup (SEL) immunity [9], [10], [11]. Anti-fuse FPGAs are preferred in outer space missions due to their high Total Ionizing Dose (TID) tolerance up to 300 krad(Si) [12]. The TID tolerance of radiation-tolerant flash-based FPGAs is about 30 krad(Si) [13]. However, because of lower cost and better flexibility due to the reprogrammability, flash-based FPGA can be used in the missions in low earth orbits.

W. Hisong's studied the area tradeoffs of four different designs of TDCs implemented in the Actel FPGA A3PE1500 [14]. According to the test results, when using the delay line method, a resolution of 540 ps was achieved employing buffers as delay elements. Hisong claimed that the resolution could be improved to 130 ps using the routing lines rather than the buffers in the FPGA.

TDCs implemented in both industry grade flash-based and anti-fuse FPGAs are described in this paper. The time interpolating method is employed in the design, and the delay element is a CMOS buffer in a flash-based FPGA, while it is a dedicated carry line in an anti-fuse FPGA. The TDC structure can be directly migrated into space-qualified FPGAs for use in future space missions.



A. TDC Architecture

The TDC in this paper is designed based on a coarse counter and a group of interpolator units [8] built by CMOS buffers in flash-based FPGAs or dedicated carry lines in anti-fuse FPGAs. Fig. 1 shows a simplified block diagram. TDCs in A3PE1500 and APA600 are fed by a reference clock of 40 MHz, and the clock frequency is 120 MHz in AX500. One single TDC channel contains an n-element time delay chain for the fine time measurement, a 16-bit coarse time counter, an encoder, and a read-out FIFO.

Figure 1
Fig. 1. Block structure of the TDC.

Once a hit signal arrives, the delay elements are sampled by the rising edge of the master clock, and the total length of the delay cells should cover at least a clock cycle. Each hit is latched by the first step and then the inverting D-flip-flop, after which a read-enable pulse is output through the AND gate to the encoder. The read-enable pulse width equals a clock period. To avoid missing the hit, each hit should be high for at least one clock period and then be low till the next clock rising edge for re-hit. When receiving the read-enable signal, the encoder unit converts the thermometer code from the delay cells to a binary code, thus the arrival time of input has a resolution equals to the least significant bit (LSB) which is 1/n of the clock period. After finishing code converting, the encoder outputs a control signal for FIFO writing. The coarse counter will give a time measurement range of about 1.6 ms at the frequency of 40 MHz and 0.53 ms at 120 MHz, respectively. More than one TDC channels may be integrated in single FPGA, thus the channel ID information can indicate which channel the hit is measured in. When receiving the FIFO write control signal, the aggregate TDC data which consists of coarse time data, fine time data and channel ID is written into the read-out FIFO.

In our design, single channel TDC using COMS buffers will occupy about 2% of the FPGA's resources in A3PE1500, while in AX500, single channel TDC using dedicated carry lines will occupy about 13% FPGA's resources.

B. Architecture of Delay Elements

Figure 2
Fig. 2. Architecture of core tile in flash-based FPGAs. (a). Core tile of APA600; (b). core tile of A3PE1500.

The core of a flash-based FPGA consists of VersaTiles. The tile structures of APA600 and A3PE1500 are shown in Fig. 2 [15], [16].

As shown in Fig. 2, the core tiles of the FPGA A3PE1500 and APA600 provide no dedicated carry lines. The tile can be configured as a CMOS buffer, which has a 670 ps time delay in A3PE1500 according to the timing simulations. In a real experiment, it gives a shorter delay time.

Figure 3
Fig. 3. Carry logic in Axcelerator anti-fuse FPGA.

Fig. 3 shows the 2-bit dedicated carry logic in anti-fuse Axcelerator (AX) FPGAs [17]. The time delay of the carry logic is about 80 ps according to timing simulation. In our design, the CMOS buffer and the dedicated carry logic are both used as delay element in the TDC.



A prototype board based on Actel FPGAs has been designed with a Universal Serial Bus (USB) port. The TDCs are implemented in the Actel FPGAs A3PE1500, APA600 and AX500, respectively. Fig. 4 shows a photograph of the prototype. In the prototype, the input signals are digitized into LVDS level by the discriminators located near the Sub Miniature version A (SMA) socket at the top. The flash-based FPGAs are configured via the JTAG ports on the board, and the anti-fuse FPGA is configured off-board using a Silicon Sculptor 3 programmer [18]. The A3PE1500 FPGA manages data transmissions of the prototype, and the TDC data is transmitted through the USB port to a data processing computer. 8 channels TDCs utilizing CMOS buffers are implemented respectively in A3PE1500 and APA600, while in AX500, 4 channels TDCs using dedicated carry lines are implemented. The power consumption of single TDC channel, including one discriminator, is about 50 mW.

Figure 4
Fig. 4. Photograph of the prototype board. FPGAs from left to right: AX500, A3PE1500, APA600.

Tests results of the three Actel FPGA-based TDCs in our prototype are shown in the following section which presents the main performance of the TDC board.

A. Performance of TDCs in A3PE1500 and APA600

Differential non-linearity and time resolution are the most important parameters of the TDCs. The “code-density test” method [19] was adopted to evaluate the non-linearity, and time resolution was evaluated by “cable-delay test” [19], [20].

In this design, the linearity is mainly limited by the logic architecture of the Actel FPGA, including the unequal clock delays and the non-uniformity of the delay chain elements. Differential non-linearity (DNL) is defined as the deviation of the TDC bin size from its normal LSB value, and the integral non-linearity (INL) is the deviation of the input/output curve from the ideal transfer characteristic, which is a straight best fitting line.

In the “code-density test”, over Formula$10^{6}$ random hits (e.g. from a pulse generator with a repetitive frequency unrelated to the TDC reference clock) were applied to one TDC channel, and the distribution of measured time data was plotted. Deviations from a flat distribution indicate the amount of differential non-linearity. The results of the code-density tests for the TDC in A3PE1500 are shown in Fig. 5(a), (b) and (c). The averaged TDC bin size is 427 ps. The DNL and INL pattern can be calculated using the bin size data. The DNL is within −0.11/+0.15 LSB, and the INL is within −0.25/+0.24 LSB. The INL and DNL repeat every clock period in the entire TDC dynamic range, and the INL correction look-up tables (LUT) can be loaded to calibrate the TDC outputs.

Figure 5
Fig. 5. Test results of the TDC in A3PE1500. (a) Bin size of a single TDC channel; (b) DNL of a single TDC channel; (c) INL of a single TDC channel; (d) Resolution after compensation.

In the “cable-delay test”, two channels of the TDC are fed by pulses with a fixed time interval. The root mean square (RMS) value of the measured distribution of the time interval, divided by Formula$\sqrt{2}$, is a measurement of the achievable single channel resolution of the TDC. Fig. 5(d) shows the histogram drawing from the distribution of one of the time resolution test results after INL compensation, the RMS of the time interval measurement is about 179.82 ps, and the resolution marked in the figure is Formula$179.82/\sqrt{2}=127\ {\rm ps}$, which stands for the resolution of single TDC channel.

Figure 6
Fig. 6. Test results of the TDC in APA600. (a) Bin size of a single TDC channel; (b) DNL of a single TDC channel; (c) INL of a single TDC channel; (d) resolution after compensation.
Figure 7
Fig. 7. Test results of the TDC in A3PE1500. (a). Bin size of a single TDC channel; (b). DNL of a single TDC channel; (c). INL of a single TDC channel; (d) resolution after compensation.

The results of code-density tests and cable-delay tests for the TDC in APA600 are illustrated in Fig. 6. The averaged bin size is 758 ps, while the DNL is within −0.06/+0.05 LSB, and the INL is within −0.06/+0.14 LSB. The single channel resolution after compensation is about 225 ps. According to the results above, using CMOS buffers as the delay elements, TDCs implemented in flash-based FPGAs A3PE1500 and APA600 show similar performance.

B. Performance of TDCs in AX500

Using dedicated carry lines as the delay elements, TDC implemented in AX500 can achieve a higher resolution compared to that in flash-based FPGAs. Fig. 7 is the results of code-density tests and cable-delay tests. The TDC has a single channel resolution of about 37 ps RMS or 74 ps averaged bin size. The DNL of the TDC is within −1/+1 LSB, and the INL is within −0.8/+1.7 LSB.

C. Performance of Measuring Different Time Intervals

The measurement RMS may change with the time intervals in the “cable delay test”. However, the maximum length of cables is limited because long cables would lead to the attenuation of the input signal and slow the leading edge, which will introduce the measurement errors. To explore a wider time range in the time interval measurement, a dual channel arbitrary function generator Tektronix AFG3252 was employed. Since the two channels of the generator can output cognate signals with adjustable delays, a wider time range can be applied in the test.

As mentioned above, TDCs in flash-based FPGAs A3PE1500 and APA600 perform similarly, thus only the features using A3PE1500 are shown in the following results. Fig. 8 shows the resolutions when measuring different time intervals within two clock periods. After INL compensation, single channel resolutions are improved from 270 to 140 ps RMS in A3PE1500, and the improvement is 75 to 40 ps RMS in AX500. Resolutions periodically repeat at every clock period under the INL pattern of each TDC. Thus in practical applications, INL look-up tables should be employed for higher precision if necessary.

Figure 8
Fig. 8. Time resolutions for various time intervals. Triangle: before INL compensation, square: after INL compensation. The tests above are performed at a given ambient temperature 25°C. (a) Resolutions of the TDC in A3PE1500; (b). Resolutions of the TDC in AX500.

D. Performance in Different Temperatures

The TDC averaged bin size has a temperature dependence, and tests for bin sizes at different temperatures have been performed. The results are illustrated in Fig. 9.

Figure 9
Fig. 9. Bin size drifts for varying temperature. (a) Bin size drifting for the TDC in A3PE1500; (b) bin size drifting for the TDC in AX500.

Using a variable temperature controlled box, the ambient temperature is changed from Formula$-21^{\circ}{\rm C}$ to Formula$+71^{\circ}{\rm C}$. Test results show that averaged bin size of the TDC in A3PE1500 increases from 413.6 ps to 456 ps by about 0.56 Formula${\rm ps}/^{\circ}{\rm C}$, and 69.6 ps to 78.5 ps by 0.1 Formula${\rm ps}/^{\circ}{\rm C}$ in AX500. Since the cell delay is a linear function of temperature, thus the LSB dependence on temperature can be established: Formula TeX Source $$\eqalign{{\rm LSB}_{({\rm A}3{\rm PE}1500)}=&\,427\ {\rm ps}+0.56\ {\rm ps}/^{\circ}{\rm C}\times({\rm T}-25^{\circ}{\rm C});\cr{\rm LSB}_{({\rm AX}500)}=&\,73.7\ {\rm ps}+0.1\ {\rm ps}/^{\circ}{\rm C}\times({\rm T}-25^{\circ}{\rm C}).}$$

Since the element delay varies with temperature, time resolution should be tested at different temperatures, and Fig. 10 shows the resolution of TDCs ranging from Formula$-21^{\circ}{\rm C}$ to Formula$+71^{\circ}{\rm C}$.

Figure 10
Fig. 10. Time resolution at different temperatures. Triangle: before temperature compensation, circle: after temperature compensation. (a) Resolution of the TDC in A3PE1500; (b) resolution of the TDC in AX500.

As shown above, the resolution becomes worse when the ambient temperature departs from 25°C. When using the appropriate element delays at each temperature, the temperature compensation is applied, and resolutions of TDCs in A3PE1500 and AX500 both return to normal values. Thus a temperature compensation mechanism which contains look-up tables created at different temperatures is necessary, so that the tap delay can be corrected at a given operating temperature.

The FPGA chips used in the prototype are industry grade, and TDCs implemented in the FPGAs provide stable performance in a temperature range of −21/Formula$+71^{\circ}{\rm C}$ according to the test results of bin sizes and resolutions at different temperatures. The TDC performance should be sufficient for the requirements of normal space missions when including temperature control.



A. Dead Time

The TDC described above is implemented using pipeline techniques, and time measurement is performed step by step. Thus the dead time of the TDC is mainly affected by the hit pulse width limitation and the re-hit time. The maximum dead time is in fact the input pulse width plus one clock period.

B. Cell Delays of Flash-Based FPGAs

The VersaTiles in flash-based FPGAs can be configured as different combinatorial modules which have different cell delays. Table I shows the various TDC bin size and single channel resolutions when employing different combinatorial cells as delay elements. The tests have been done using A3PE1500.

Table 1

C. Cell Placement

Delay cell placement in this design can of course, be performed manually, but it will be very time-consuming. The “Chip planner” in Actel Libero IDE software provides an easy method for cell placement [21]. By adding placement constraints in the design, the delay cells are placed closely in a queue, and the latching D-flip-flops are placed next to the delay cells, making sure that the delay chain provides the best linearity.

D. Coarse Counter and Clock Frequency

The delay line length can be shortened by raising the operating clock frequency. The encoder complexity can also be reduced accordingly. However, in flash-based FPGAs, the coarse counter is formed by combinatorial cells, and the carry delay is longer than the delay of the dedicated carry lines. Once the clock frequency is raised to 100 MHz, bit carrying must be finished in 10 ns, thus a cell place constraint must be added in “chip planner” to avoid obtaining the wrong coarse time. All the cells of coarse counter should be placed in a small region to shorten routing line delays. In the anti-fuse FPGA AX500, the coarse counter uses dedicated carry lines for carrying bit, thus a 120 MHz frequency clock is available.

Output of the coarse counter is added by ‘1’ at every clock rising edge. Thus in order to obtain correct coarse time, in the TDC implemented in flash-based FPGAs, coarse time should be written into the FIFO at clock rising edge when receiving the control signal, and on the contrary, in the TDC implemented in AX500, coarse time should be written at the clock falling edge.

E. Part-to-Part Variations and Voltage Effect on Cell Delay

Part-to-part variations of FPGAs would lead to the TDC performance variations, thus the bin size and non-linearity information must be re-calibrated through the “code-density test” when using different FPGAs.

Cell delay of the TDC changes not only with temperature, but also with the internal supply voltage. Lower supply voltage would lead to longer cell delays. Low dropout (LDO) regulators in this design can provide stable and low noise power supplies, making the voltage effect negligible.



TDCs based on interpolating technique were implemented in three Actel FPGAs: A3PE1500, APA600, and AX500. Tests were finished at the beginning of 2012. With anti-fuse FPGA AX500, using dedicated carry lines as the delay elements, the highest resolution of 37 ps RMS and an averaged 73.7 ps bin size was achieved. When employing CMOS buffers in flash-based FPGAs, the resolution was about 127 ps RMS with 427 ps bin size in A3PE1500, and 225 ps RMS with 758 ps bin size in APA600. The TDC bin size changed linearly with temperature, and INL look-up tables for different temperatures were needed to compensation. Both TDCs in the flash-based and the anti-fuse FPGAs showed temperature stability in a temperature range of −21/Formula$+71^{\circ}{\rm C}$. Identical TDC structures were available in Actel's space qualified FPGAs, could possibly be used in future space missions.


The authors would like to thank T. Zhang from the Department of Geophysics and Planetary Sciences, USTC, and S. Barabash from the Swedish Institute of Space Physics for their helpful discussions and suggestions regarding this work.


This work was supported by the Fundamental Research Funds for the Central Universities (No. WK2030040023 and No. WK2030040015), and by the Strategic Pioneer Program on Space Science, Chinese Academy of Sciences under Grant No.XDA04070900.

The authors are with the State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China (e-mail:

Color versions of one or more of the figures in this paper are available online at


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Xi Qin

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Changqing Feng

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Deliang Zhang

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Bin Miao

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Lei Zhao

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Xinjun Hao

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