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A Rigorous 3-D NAND Flash Cost Analysis

Figure 1

Figure 1
A 3-D rendition of a vertical cylindrical NAND Flash with 48 cells distributed over 4 device layers. Horizontal gates are shown in semi-transparent red, and vertical channels are shown in green encased in dark grey sheaths of memory dielectric.

Figure 2

Figure 2
A plan view of the cell array showing the X and Y cell pitches.

Figure 3

Figure 3
The side view of the memory stack showing the cell pitch in the X direction.

Figure 4

Figure 4
The side view of the memory stack showing the cell pitch in the Y direction along with the key structural parameters used in the die size and cost model.

Figure 5

Figure 5
128 Gbit die size as a function of the number of device layers in the vertical channel stack with taper angle Formula$\theta$ as a parameter. Model constants are given in the inset and are based on [8] except for the array efficiency Formula${AE}_{0}$ and the slit's short side dimension at its bottom, Formula${\rm D}_{\rm B}$ values of which are estimated but can be adjusted by the interested reader.

Figure 6

Figure 6
128 Gbit die size as a function of the number of device layers in the vertical channel stack with vertical gate pitch Formula$\left({{L}_{g}+{L}_{s}}\right)$ as a parameter. The taper angle has been kept constant at one degree. All other model constants are as in Fig. 5.

Figure 7

Figure 7
128 Gbit die cost as a function of the number of device layers in the vertical channel stack with taper angle as a parameter. Model constants are given in the inset. Vertical gate pitch is held at 40 nm.

Figure 8

Figure 8
128 Gbit die cost as a function of the number of device layers in the vertical channel stack with vertical gate pitch Formula$\left({{L}_{g}+{L}_{s}}\right)$ as a parameter. Model constants are given in the inset. Taper angle is held at one degree.

Figure 9

Figure 9
256 Gbit die size as a function of the number of device layers using a vertical channel NAND with taper angle as a parameter. Model constants are given in the inset. Vertical gate pitch is held at 40 nm.

Figure 10

Figure 10
256 Gbit die size as a function of the number of device layers using a lateral lithography-intensive approach with minimum cell feature size, F, as a parameter. Model constants are given in the inset.

Figure 11

Figure 11
256 Gbit die cost as a function of the number of device layers using a vertical channel NAND approach with taper angle as a parameter. Model constants are given in the inset. Vertical gate pitch is held at 40 nm.

Figure 12

Figure 12
256 Gbit die cost as a function of the number of device layers using a lithography-intensive 3-D approach with minimum feature size, F, as a parameter. Model constants are given in the inset.