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• Abstract

SECTION I

INTRODUCTION

In this paper, we propose and simulate 160-Gbit/s simultaneous optical half-adder and half-subtracter based on a single slot waveguide. Two types of nonlinear materials, i.e., silicon-nanocrystal (Si-nc) and poly-[2,4 hexadiyne-1,6 diol-bis-($p$-toluene sulfonate)] (PTS), are considered as slot region for comparison. Temporal waveforms, eye diagrams, quality $(Q)$ factor, extinction ratio $(ER)$ and eye opening $(EO)$ are calculated and analyzed to evaluate the operation performance. The performance dependence on the waveguide length and input power are also studied and optimized.

SECTION II

STRUCTURE AND MODELING OF SLOT WAVEGUIDE

The horizontal slot waveguide features a sandwich structure, which has a thin slot layer of low-refractive-index material surrounded by upper and lower layers of high-refractive-index materials. As shown in Fig. 1(a), the high-refractive-index layers are silicon (Si) and the low-refractive-index slot layer can be silicon nanocrystal (Si-nc or Si-rich) [33], [34], chalcogenide glasses [35] or organic materials [32], [36], [37] with high nonlinearity. The cladding is air and the substrate is silica $(\hbox{SiO}_{2})$. The typical structure parameters are as follows: waveguide width ${\rm W} = 250\ \hbox{nm}$, upper silicon height ${\rm H}_{\rm u} = 180\ \hbox{nm}$, lower silicon height ${\rm H}_{\rm l} = 180\ \hbox{nm}$, slot height ${\rm H}_{\rm s} = 25\ \hbox{nm}$, and silica substrate height is 2 $\mu\hbox{m}$. Due to the index difference between high-refractive-index and low-refractive-index layers, the electric field of quasi-TM mode (vertically polarized) at the interfaces of silicon and slot layers is discontinuous, leading to an enhanced light concentration in the thin slot layer. The cross section of quasi-TM mode distribution of the slot waveguide is shown in Fig. 1(b). Fig. 1(c) and (d) depict the normalized power density along the $X$ and $Y$ directions. One can clearly see that the light is tightly confined in the thin slot region. The well-confined light together with large nonlinear coefficient of slot material offers enhanced nonlinearity potentially used for efficient optical digital signal processing.

Fig. 1. (a) 3D schematic structure, (b) mode distribution, and (c), (d) normalized power density along $X$ and $Y$ directions for the proposed slot waveguide.

In addition to the tight light confinement, another challenge is to choose appropriate slot material with desired properties (e.g., high nonlinearity, low two-photon absorption (TPA)). As well known, the real and imaginary parts of nonlinear coefficient $\gamma$ are related to the Kerr nonlinear index of refraction ${\rm n}_{2}$ and the TPA coefficient $\beta_{\rm TPA}$, respectively. Compared with $\hbox{SiO}_{2}$ and Si, Si-nc and PTS have relatively large Kerr nonlinear index of refraction. For Si-nc with 8% Si excess and annealed at 800 °C, ${\rm n}_{2} = 4.8 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}$ and $\beta_{\rm TPA} = 7 \times 10^{-11}\ \hbox{m/W}$ at 1550 nm [29], [33]. For PTS, ${\rm n}_{2} = 6.25 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}$ and $\beta_{\rm TPA} \approx 0$ at 1550 nm [37]. In the simulations, both Si-nc and PTS are employed as slot materials for comparison. We calculate the mode effective index, mode effective area, chromatic dispersion, and nonlinearity of the guided mode in the proposed slot waveguide by using a full-vector finite-element mode solver (COMSOL Multiphysics). Nonlinear coefficient $\gamma$ is computed using a full-vector model in which the contributions of different materials (e.g., Si-nc/PTS, Si) to nonlinearity are weighted by optical mode distribution [38]. Over a wavelength range from 1000 to 1700 nm, the material refractive index lies in (1.72, 1.725) for Si-nc and (1.7255, 1.869) for PTS. As shown in Fig. 2(a), material dispersions obtained from Sellmeier equations for Si-nc [30] and PTS [36] are taken into consideration. It is noted that the dispersion keeps almost unchanged for Si-nc while decreases with the increase of wavelength for PTS. Material dispersions for $\hbox{SiO}_{2}$ and Si are also considered. In order to ensure the accuracy of simulations, the convergence of the calculated chromatic dispersion is verified. As shown in Fig. 2(b), we calculate the chromatic dispersion at 1550 nm by varying the element size from 30 to 1 nm in the slot region. When the element size set in the slot region is small enough (< 5 nm), negligible changes are observed in the calculated chromatic dispersion values. Hence, it is expected that an element size of 5 nm is precise enough for achieving accurate calculations.

Fig. 2. (a) Material dispersions for Si-nc and PTS. (b) Calculated chromatic dispersion at 1550 nm as a function of the element size set in the slot region.
SECTION III

CONCEPT AND PRINCIPLE OF HALF-ADDER AND HALF-SUBTRACTER

Fig. 3 depicts the gate-level conceptual diagram and the logical truth table for half-adder and half-subtracter using conventional electronic gate symbols. Half-adder and half-subtracter are fundamental binary arithmetic units. As shown in Fig. 3, for two binary inputs $(A, B)$, half-adder offers two binary outputs of Sum $(A \oplus B = \bar{A} \cdot B + A \cdot \bar{B})$ and Carry $(A \cdot B)$, while half-subtracter provides two binary outputs of Difference $(A\oplus B)$ and Borrow ($A \cdot \bar{B}$ or $B \cdot \bar{A}$). As shown in Fig. 3, it is found that the Sum of half-adder and the Difference of half-subtracter take the same output. The output Sum/Difference is logical “0” only when both of the two inputs $(A, B)$ are logical “0” or “1”, corresponding to the logical XOR function $(A \oplus B)$. The output Carry of half-adder is logical “1” only when both of two inputs are logical “1”, corresponding to the logical AND function $(A \cdot B)$. The output Borrow for $A - B$ of half-subtracter is logical “1” only when input $A$ is logical “0” and input $B$ is logical “1”, corresponding to the logical $\bar{A} \cdot B$ function. The output Borrow for $B - A$ of half-subtracter is logical “1” only when input $A$ is logical “1” and input $B$ is logical “0”, corresponding to the logical $A \cdot \bar{B}$ function.

Fig. 3. Digital gate-level diagram and logical truth table for half-adder and half-subtracter.

To implement compact simultaneous half-adder and half-subtracter, multiple outputs $A \cdot B$, $\bar{A} \cdot B$ and $A \cdot \bar{B}$ are expected for two input signals $A$ and $B$, which can be achieved by exploiting TDFWM in a single slot waveguide. As shown in Fig. 4(a), the operation principle relies on two degenerate four-wave mixing (FWM) processes called TDFWM. For two input signals (signal $A$ at $\lambda_{\rm SA}$, signal $B$ at $\lambda_{\rm SB}$), two converted idlers (idler 1 at $\lambda_{{\rm i}1}$, idler 2 at $\lambda_{{\rm i}2}$) are generated by two degenerate FWM processes. In the first degenerate FWM process involving signal $A$, signal $B$ and idler 1, the photons of signal $A$ are annihilated and transferred to the photons of idler 1 and signal $B$. In the second degenerate FWM process involving signal $A$, signal $B$ and idler 2, the photons of signal $B$ are consumed and converted to the photons of idler 2 and signal $A$. It is possible to deplete both of the two signals which are converted to two idlers by appropriately controlling the power of two signals. As shown in Fig. 4(b), owing to such parametric depletion effect of TDFWM, output signals at $\lambda_{\rm SA}$ and $\lambda_{\rm SB}$ from the slot waveguide take logical results of $A \cdot \bar{B}$ and $\bar{A} \cdot B$, corresponding to the Borrow outputs for $B - A$ and $A - B$ of half-subtracter, respectively. In addition, both of the two converted idlers at $\lambda_{{\rm i}1}$ and $\lambda_{{\rm i}2}$ take logical AND result of $A \cdot B$, corresponding to the Carry output of half-adder. Moreover, the combination of $A \cdot \bar{B}$ and $\bar{A} \cdot B$ produces logical XOR result of $A\oplus B = \bar{A} \cdot B + A \cdot \bar{B}$, corresponding to the Sum output of half-adder and Difference output of half-subtracter. Hence, single slot waveguide based simultaneous half-adder and half-subtracter are achievable.

Fig. 4. (a) Illustration of twin degenerate four-wave mixing (TDFWM) and (b) principle of single slot waveguide based simultaneous half-adder and half-subtracter.
SECTION IV

RESULTS AND DISCUSSIONS

The proposed single slot waveguide based half-adder and half-subtracter are simulated using nonlinear coupled-mode equations under the slowly varying envelope approximation. Group-velocity mismatching (GVM), group-velocity dispersion (GVD), TPA, free-carrier absorption (FCA), and free-carrier dispersion (FCD) are considered. In the following simulations, two synchronized independent input signals $A$ and $B$ are assumed to be 160-Gbit/s $2^{13} - 1$ pseudo-random binary sequence (PRBS) return-to-zero (RZ) data signals with a hyperbolic-secant pulse shape and a 6.25-ps pulse width. The wavelengths of input signals $A$ and $B$ are set at 1548 and 1552 nm, respectively. The wavelengths of two idlers generated by TDFWM are around 1546 and 1554 nm, respectively. Two different nonlinear materials, i.e., Si-nc $({\rm n}_{2} = 4.8 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} = 7 \times 10^{-11}\ \hbox{m/W})$ and PTS $({\rm n}_{2} = 6.25 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} \approx 0)$, are considered as the low-refractive-index slot region for comparison. Slot waveguide employing Si-nc or PTS can offer greatly enhanced nonlinearity due to its intrinsic large Kerr nonlinear index of refraction. By properly optimizing the structure parameters of the proposed slot waveguide $({\rm W} = 250\ \hbox{nm}, {\rm H}_{\rm u} = 180\ \hbox{nm}, {\rm H}_{\rm l} = 180\ \hbox{nm}, {\rm H}_{\rm s} = 25\ \hbox{nm})$, small effective mode area and high nonlinearity of 0.077 $\mu\hbox{m}^{2}$ and 4400 $\hbox{W}^{-1}\cdot\hbox{Km}^{-1}$ at 1550 nm for Si-nc slot waveguide while 0.077 $\mu\hbox{m}^{2}$ and 5400 $\hbox{W}^{-1}\cdot\hbox{Km}^{-1}$ at 1550 nm for PTS slot waveguide are achievable.

We first calculate and compare the operation performance of Si-nc slot waveguide and PTS slot waveguide based half-adder and half-subtracter under the same waveguide length of 3.5 mm and peak power of input signal of 320 mW.

Fig. 5 depicts simulation results of temporal waveforms and eye diagrams for 160-Gbit/s half-adder and half-subtracter using a single Si-nc slot waveguide. Typical 20-bit sequences of two independent input data streams $A$ at $\lambda_{\rm SA}$ and $B$ at $\lambda_{\rm SB}$ are shown in Fig. 5(a) and (b). Fig. 5(c) and (d) show the corresponding 20-bit sequences of two output signals from the Si-nc slot waveguide at $\lambda_{\rm SB}$ and $\lambda_{\rm SA}$, respectively. When both of the two input signals at $\lambda_{\rm SA}$ and $\lambda_{\rm SB}$ are logical “1”, one can clearly observe the parametric depletion effect, which indicates logical results of $\bar{A} \cdot B$ and $A \cdot \bar{B}$ carried by the two output signals from the Si-nc slot waveguide at $\lambda_{\rm SB}$ and $\lambda_{\rm SA}$, corresponding to the Borrow outputs for $A - B$ and $B - A$ of half-subtracter, respectively. The Sum output of half-adder and the Difference output of half-subtracter are shown in Fig. 5(e) by combining two output signals $(A \cdot \bar{B} + \bar{A} \cdot B)$ to form the logical XOR function. The Carry output of half-adder corresponds to converted idlers $(\lambda_{{\rm i}1}, \lambda_{{\rm i}2})$, as shown in Fig. 5(f) and (g), in which the converted idlers take logical “1” only when both of the two input signals at $\lambda_{\rm SA}$ and $\lambda_{\rm SB}$ are logical “1”. The calculated temporal waveforms shown in Fig. 5(a)(g) imply that single Si-nc slot waveguide based half-adder and half-subtracter are successfully implemented. Fig. 5(h)(n) display simulated eye diagrams corresponding to Fig. 5(a)(g), respectively. To evaluate the operation performance, we define following three factors of quality factor $(Q)$, extinction ratio $(ER)$ and eye opening $(EO)$ TeX Source \eqalignno{Q = &\, 20\log_{10} \left[(P_{1avg} - P_{0avg})/(\sigma_{1} + \sigma_{0})\right]&\hbox{(1)}\cr ER = &\, 10\log_{10}(P_{1avg}/P_{0avg})&\hbox{(2)}\cr EO = &\, (P_{1\min} - P_{0\max})/(P_{1avg} - P_{0avg})&\hbox{(3)}} where $P_{1avg}$ and $P_{1\min}$ are average and minimum power of logical “1” while $P_{0avg}$ and $P_{0\min}$ average and maximum power of logic “0”. $\sigma_{1}$ and $\sigma_{0}$ are standard deviations of logical “1” and “0”. The calculated values of $Q$, $ER$, and $EO$ are marked in Fig. 5.

Fig. 5. (a)–(g) Temporal waveforms and (h)–(n) eye diagrams for single Si-nc slot waveguide based 160-Gbit/s half-adder and half-subtracter.

For comparison, we also show simulated results in Fig. 6 for 160-Gbit/s half-adder and half-subtracter using a single PTS slot waveguide. The temporal waveforms of input signals and output signals and idlers are depicted in Fig. 6(a)(g), respectively, showing the successful implementation of single PTS slot waveguide based half-adder and half-subtracter. Fig. 6(h)(n) depict simulated eye diagrams with marked values of $Q$, $ER$, and $EO$ corresponding to Fig. 6(a)(g), respectively.

Fig. 6. (a)–(g) Temporal waveforms and (h)–(n) eye diagrams for single PTS slot waveguide based 160-Gbit/s half-adder and half-subtracter.

In order to present a comprehensive performance evaluation, GVM, GVD, TPA, FCA, and FCD effects are taken into consideration. However, the simulation results show dominant roles of TPA and FCA degrading the operation performance, while GVM, GVD, and FCD effects induce negligible performance degradation owing to the short waveguide length ($\sim$ mm). Furthermore, by carefully comparing the obtained results for 160-Gbit/s half-adder and half-subtracter using Si-nc slot waveguide and PTS slot waveguide, one can clearly see from the eye diagrams that: 1) the performance of output Sum/Difference, Carry, and Borrow is degraded compared with input signals; 2) PTS slot waveguide features superior performance compared with Si-nc slot waveguide under the same waveguide length (3.5 mm) and peak power of input signal (320 mW). Such phenomena can be briefly explained as follows. First, the degraded “1” level in the eye diagrams comes from the pattern effect after passing through the slot waveguide, which is assumed to be mainly caused by the FCA effect. Second, the degraded “0” level in the eye diagrams comes from the residual power, which is due to incomplete depletion during the TDFWM parametric process. Third, for two different slot materials of Si-nc $({\rm n}_{2} = 4.8 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} = 7 \times 10^{-11}\ \hbox{m/W})$ and PTS $({\rm n}_{2} = 6.25 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} \approx 0)$, PTS offers higher Kerr nonlinear index of refraction and negligible TPA coefficient, featuring better performance for 160-Gbit/s half-adder and half-subtracter, i.e. enhanced depletion (“0” level) and alleviated pattern effect (“1” level). Even using PTS slot waveguide with $\beta_{\rm TPA} \approx 0$, one may still see the non-negligible pattern effect in the “1” level of eye diagrams owing to $\beta_{\rm TPA}$—dependent FCA. This is because of the FCA in Si layers with partial mode distribution, which is also considered in full-vector model simulations when calculating nonlinearities by mode distribution weight [38]. For the two examples shown in Figs. 5 and 6, it is shown that higher Kerr nonlinear index of refraction of PTS plays a dominant role for achieving improved operation performance.

Remarkably, slot waveguide based half-adder and half-subtracter involve many parameters which could impact on the operation performance. In addition to the parameters dependent on the adopted materials such as Kerr nonlinear index of refraction and TPA coefficient, other parameters related to geometric structures and incident conditions such as cross section geometry, waveguide length, input power, are also of great importance to be considered when comprehensively optimizing the operation performance.

We further study the operation performance for Borrow outputs $(A - B, B - A)$ of half-subtracter and Sum/Difference output of half adder/half-subtracter as functions of the waveguide length and peak power of input signal. The calculated $Q$ factors for Borrow $(A - B)$, Borrow $(B - A)$ and Sum/Difference are shown in Fig. 7(a)(c). One can clearly see that $Q$ factor increases with the increase of waveguide length (0 $\sim$ 4 mm) and peak power of input signal (30 $\sim$ 350 mW). The calculated $ER$ and $EO$ for Borrow $(A - B)$, Borrow $(B - A)$ and Sum/Difference are shown in Fig. 7(d)(i), respectively. Similar trends for $ER$ and $EO$ are obtained as increasing the waveguide length (0 $\sim$ 4 mm) and peak power of input signal (30 $\sim$ 350 mW). Moreover, Fig. 7 also offers an easy to follow theoretical basis for performance optimization. For desired values of $Q$, $ER$ and $EO$, one can clearly find available region of waveguide length and peak power of input signal from Fig. 7. For instance, the white lines in Fig. 7(a)(i) correspond to $Q = 20\ \hbox{dB}$, $ER = 10\ \hbox{dB}$, and $EO = 0.9$, respectively. Hence, one can choose waveguide length and peak power of input signal from the region above the marked white lines if better performance is expected ($Q\ >\ 20\ \hbox{dB}$, $ER\ >\ 10\ \hbox{dB}$, and $EO\ >\ 0.9$).

Fig. 7. Calculated (a)–(c) $Q$-factor, (d)–(f) extinction ratio $(ER)$, and (g)–(i) eye opening $(EO)$ for Borrow outputs $(A - B, B - A)$ of half-subtracter and Sum/Difference output of half adder/half-subtracter as functions of the waveguide length and peak power of input signal. The white lines mark $Q = 20\ \hbox{dB}$ in (a)–(c), $ER = 10\ \hbox{dB}$ in (d)–(f), and $EO = 0.9$ in (g)–(i).

For the proposed simultaneous half-adder and half-subtracter, two input signals $(A, B)$ are fed into a single slot waveguide, and the combined parametric depletion and wavelength conversion effects inside the slot waveguide can offer multiple outputs $(A \cdot \bar{B}, B \cdot \bar{A}, A \cdot B)$. As a consequence, half-adder can be obtained by choosing some of the outputs (SUM: $A\oplus B = \bar{A} \cdot B + A \cdot \bar{B}$, CARRY: $A \cdot B$). Meanwhile, choosing some other outputs can enable half-subtracter (DIFF: $A\oplus B = \bar{A} \cdot B\ + A \cdot \bar{B}$, BORROW: $A \cdot \bar{B}$, $B \cdot \bar{A}$). However, wavelength demux and multiple use of common outputs are desired for practical implementations of simultaneous half-adder and half-subtracter. For instance, wavelength demux is required after the waveguide to discriminate different wavelengths $(\lambda_{\rm SA}, \lambda_{\rm SB}, \lambda_{i1}, \lambda_{i2})$. Also, splitters are needed to divide $\lambda_{\rm SA}$ into two and also $\lambda_{\rm SB}$ into two, which can be used for BORROW $(A \cdot \bar{B}, B \cdot \bar{A})$. In addition, the combination of $\lambda_{\rm SA}$ and $\lambda_{\rm SB}$ by a coupler provides SUM/DIFF $(A \oplus B = \bar{A} \cdot B + A \cdot \bar{B})$. The challenge is the compatibility of desired wavelength demux and splitter/coupler with slot waveguide. Fortunately, wavelength demux and splitter/coupler fabricated on silicon-on-insulator (SOI) platform have been reported [39], [40], [41], which is compatible with the slot waveguide. In this scenario, on-chip simultaneous half-adder and half-subtracter using a single slot waveguide together with wavelength demux and splitter/coupler is achievable. Note that the SUM/DIFF corresponds to the combination of two output signal wavelengths. Using two combined wavelengths is not feasible for further cascadability of logic gates to construct advanced logic operations. A potential solution could be using XPM to transfer the $A\oplus B = \bar{A} \cdot B + A \cdot \bar{B}$ from two wavelengths $(\lambda_{\rm SA}, \lambda_{\rm SB})$ to a single new wavelength [42], [43].

SECTION V

CONCLUSION

We have proposed and numerically demonstrated a simple scheme of simultaneous optical half-adder and half-subtracter at 160-Gbit/s using parametric depletion effect of TDFWM in a single slot waveguide. The employed waveguide structure guiding the light in the slot region features well-confined light concentration and resultant enhanced nonlinearity. Two output signals after parametric depletion provide the Borrow of half-subtracter $A - B$ and $B - A$. The combination of two output signals corresponds to the Sum of half-adder $(A + B)$ and Difference of half-subtracter $(A - B, B - A)$. Two generated idlers by TDFWM offer the Carry of half-adder $(A \cdot B)$. The operation performance of half-adder and half-subtracter has been analyzed in terms of $Q$-factor, $ER$ and $EO$. The performance degradation of output Sum/Difference, Carry and Borrow could be ascribed to the FCA effect and incomplete depletion. We have employed two different nonlinear materials of Si-nc $({\rm n}_{2} = 4.8 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} = 7 \times 10^{-11}\ \hbox{m/W})$ and PTS $({\rm n}_{2} = 6.25 \times 10^{-17}\ \hbox{m}^{2}/\hbox{W}, \beta_{\rm TPA} \approx 0)$ as the slot region for comparison. We have found that: 1) PTS slot waveguide shows better performance compared with Si-nc slot waveguide under the same waveguide length (3.5 mm) and peak power of input signal (320 mW). 2) Larger ${\rm n}_{2}$ of PTS plays a dominant role for gaining superior performance. Furthermore, we have also investigated the operation performance of half-adder and half-subtracter as functions of the waveguide length and peak power of input signal, presenting an easy way to choose appropriate wavelength length and input power for desired performance. With future improvement, more advanced and complicated digital signal processors are expected to be explored, such as full-adder, full-subtracter, etc.

Footnotes

This work was supported by the National Natural Science Foundation of China (NSFC) under Grants 61222502 and 61077051, the Program for New Century Excellent Talents in University under Grant NCET-11-0182, and the Fundamental Research Funds for the Central Universities (HUST) under Grants 2013022 and 2013ZZGH003. Corresponding author: J. Wang (e-mail: jwang@hust.edu.cn).

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