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SECTION I

THE increasing demand for powerful electronic devices resulted in a growing need for large scale mixed-signal system-on-chips (SoCs), requiring the integration of digital circuits and analog/RF circuits on the same chip [1]. Analog/RF circuits in mixed-signal SoCs, however, often suffer from performance deterioration because of the substrate noise generated by digital circuits. This is especially the case when CMOS processes with lightly doped substrates are used for the implementation to reduce the cost [2]. ${\rm P}^{+}$ guard ring is a layout design approach and one of the most widely used noise suppression methods in modern SoCs as it features low cost and easy implementation [2], [3]. Fig. 1 shows a generic ${\rm P}^{+}$ guard ring implemented on a typical lightly doped CMOS substrate. The aggressor contact represents the noise coupling node in digital circuits and the victim contact represents the coupling node of any analog/RF circuits on the same chip. The noise suppression performance of the guard ring is dependent on layout and substrate parameters [2], such as the aggressor-to-guard ring distance $(d_{\rm ag})$, guard ring-to-victim distance $(d_{\rm gv})$, guard ring width $(w_{g})$, resistivity/permittivity of the substrate $(\rho_{1,2}/\epsilon_{{\rm ox},1,2})$, and substrate thicknesses $(t_{{\rm ox},1,2})$.

Currently, the guard ring parameters are mainly investigated by measurements and designed based on empirical rules-of-thumb [2], [3]. However, the noise suppression level of these designs is usually unpredictable and the chip area could easily be wasted as the dependency of the noise suppression performance on guard ring parameters has not been accurately characterized. Recently, efforts have been made to find compact ${\rm P}^{+}$ guard ring models, which provide more insights into the dependency [4], [5], [6], [7]. Some of these models require fitting-factors [4], which needs calibration fixtures and therefore are unfeasible for prelayout predictions. Some of the models characterize the guard ring by dividing the guard ring into numerous small contacts/cells [5], [6], which increases the model complexity significantly. Other models failed to address the constriction resistances as well as capacitive coupling, which makes them valid only for low frequency designs on uniform or epitaxial substrates [7]. Unlike uniform or epitaxial substrates, the lightly doped substrates of standard CMOS processes have a thin P-well layer [Fig. 1(b)]. The P-well layer introduces significant current constriction effects at near fields close to the contacts [8]. Such effects cannot be effectively characterized by existing guard ring models. To obtain accurate noise suppression predictions and to help SoC designers to manage the noise issues, new guard ring models feasible for lightly doped substrates are desired.

This paper proposes a ${\rm P}^{+}$ guard ring model where constriction resistances and capacitive coupling are included. Equations are derived based on a conformal mapping approach to fully characterize the effects of the layout/substrate parameters, eliminating any fitting factors. Electromagnetic (EM) simulation and experimental verifications on DC resistances and S-parameters have been conducted as well. This paper is arranged as follows. Section II presents the proposed model. EM-simulation validation is presented in Section III, and the experimental verification as well as design guidelines are discussed in Section IV. Conclusions are drawn in Section V.

SECTION II

The proposed three port circuit network model for the guard ring in Fig. 1 is shown in Fig. 2. The proposed model includes both the resistive and capacitive couplings between the aggressor, guard ring, and victim, as represented by ports $a$, $g$ and $v$, respectively. Please note that the model does not include the interconnection of the guard ring to on-chip ground (GND). In the proposed model, $C_{\rm ag}$, $C_{\rm gv}$ denote the capacitances between the aggressor, guard ring, and victim in the oxide layer, respectively. For typical CMOS processes, where the P-well layer is significantly more conductive and two to three orders thinner than the P-substrate, the majority of the noise current flows horizontally from the aggressor to the victim in the P-well. This means, there is no current flowing into the P-substrate except at the near fields of the aggressor, guard ring, and victim. Therefore, the impedances between the aggressor/victim and guard ring are divided into two parallel parts in the P-well layer and P-substrate, e.g., $Z_{\rm aw}/Z_{\rm vw}$ and $Z_{\rm as}$, $Z_{\rm gs}/Z_{\rm vs}$, respectively. It should be noted that $Z_{\rm aw}/Z_{\rm vw}$ and $Z_{\rm as}$, $Z_{\rm gs}/Z_{\rm vs}$ represent the impedances between the dashed surfaces [Fig. 1(b)], which do not include the constriction resistances in the near field of the contacts [8]. In this paper, this error is corrected by adding $Z_{a}$, $Z_{g1-3}$, and $Z_{v}$ to characterize the current constriction effects for the aggressor, guard ring, and victim, respectively.

In consistence with in [7], the model proposed here approximates the layout of the square contacts and guard rings using circular shapes. The approximation is based on the condition that circular contacts or guard rings have the same area as the corresponding rectangular contacts and guard rings. As has been discussed in [7], the approximation error is acceptable for practical use. Thus $r_{a,v}={L_{a,v}}/{\sqrt{\pi}}$, where $r_{a}$ and $r_{v}$ are the radii of the circular contacts approximating the square aggressor and victim contact (with side length $L_{a,v}$), respectively. For a square guard ring with an outer side length of $L_{g}$ and a width of $w_{g}$, it is approximated as a circular guard ring with the outer and inner radius of $r_{g}={L_{g}}/{\sqrt{\pi}}$ and $r_{\rm gin}=({L_{g}-w_{g}})/{\sqrt{\pi}}$, respectively.

For a homogeneous medium with resistivity of $\rho$ and permittivity of $\epsilon$, there exists the relationship [9] TeX Source $$R=\rho{\epsilon}/C\eqno{\hbox{(1)}}$$ where $R$ and $C$ are the resistance and capacitance of the medium. Therefore, this paper only discusses either $R$ or $C$ in $Z_{\rm ij}$. The corresponding $C$ or $R$ can be obtained using (1). Based on the square-to-circular layout approximations the capacitance $C_{\rm ag}$ is derived as TeX Source $$C_{\rm ag}={2\pi{\epsilon_{\rm ox}t_{\rm ox}}}/{{\rm acosh}\,\left[{{1}\over{2}}\left({{D^{2}}\over{r_{a}r_{g}}}-{{r_{a}}\over{r_{g}}}-{{r_{g}}\over{r_{a}}}\right)\right]}\eqno{\hbox{(2)}}$$ where $D=d_{\rm ag}+r_{a}+r_{g}$ and $C_{\rm gv}$ is the capacitance between the lateral surfaces of a cylindric ring with inner radius $r_{v}$, outer radius $r_{\rm gin}$, and height $t_{\rm ox}$ TeX Source $$C_{\rm gv}={2\pi{\epsilon_{\rm ox}t_{\rm ox}}}/{\ln{{r_{\rm gin}}\over{r_{v}}}}\eqno{\hbox{(3)}}$$ and similarly $C_{\rm aw}$ can be derived as TeX Source $$C_{\rm aw}={2\pi{\epsilon_{1}t_{1}}}/{{\rm acosh}\,\left[{{1}\over{2}}\left({{D^{2}}\over{r_{a}r_{g}}}-{{r_{a}}\over{r_{g}}}-{{r_{g}}\over{r_{a}}}\right)\right]}.\eqno{\hbox{(4)}}$$

In practical cases, the conductivity in a P-well layer is a function of the distance to the top of the layer (Fig. 3). In this paper, the thickness of the P-well layer is defined as the conductivity drops to 10% of $\sigma_{p}-\sigma_{\rm sub}$, where $\sigma_{p}$ and $\sigma_{\rm sub}$ are the conductivities of the P-well and P-substrate, respectively. Through dividing the P-well into infinitely thin layers, uniform doping can be assumed for each layer and hence it has TeX Source $$R_{\rm aw}={{1}\over{2\pi{G}}}{{\rm acosh}\,\left[{{1}\over{2}}\left({{D^{2}}\over{r_{a}r_{g}}}-{{r_{a}}\over{r_{g}}}-{{r_{g}}\over{r_{a}}}\right)\right]}\eqno{\hbox{(5)}}$$ where TeX Source $$G=\int_{t_{\rm ox}}^{t_{1}}\sigma{(t)}dt.\eqno{\hbox{(6)}}$$ Similarly, $R_{\rm vw}$ is derived as TeX Source $$R_{\rm vw}={{1}\over{2\pi{G}}}{\ln{{r_{\rm gin}}\over{r_{v}}}}.\eqno{\hbox{(7)}}$$

Calculating $Z_{\rm as}$, $Z_{\rm gs}$, and $Z_{\rm vs}$ is different from that of $Z_{\rm aw}$ and $Z_{\rm vw}$. This is because the current in the P-substrate is spreading over a much thicker substrate and cannot be assumed to be horizontal. The spreading resistance of a circular contact on a semi-infinite substrate has been discussed in [10] and it is given as TeX Source $$R_{\rm as}={{\rho_{2}}\over{4r_{a}}}\left[1-{{2}\over{\pi}}\arcsin\left({{r_{a}}\over{r_{a}+d_{\rm ag}}}\right)\right].\eqno{\hbox{(8)}}$$ For a ${\rm P}^{+}$ guard ring on a thick substrate, the current spreads in the way similar to a circular contact at far field [11] (Fig. 4), whereas the constriction effects at the near field are different. In this paper, the far field resistance of the guard ring is calculated by treating the ring as a circular contact with a radius of $r_{g}$ TeX Source $$R_{\rm gs}={{\rho_{2}}\over{4r_{g}}}\left[1-{{2}\over{\pi}}\arcsin\left({{r_{g}}\over{r_{g}+d_{\rm ag}}}\right)\right]\eqno{\hbox{(9)}}$$ where $r_{g}=r_{\rm gin}+w_{g}$. The near field constriction effects are described by $R_{g1-3}$ (discussed in Section III) in Fig. 2. Different from the aggressor, the victim is inside the guard ring. Thus, $R_{\rm vs}$ is the resistance between the victim and the equipotential surface at distance of $d_{\rm gv}$ TeX Source $$R_{\rm vs}={{\rho_{2}}\over{4r_{g}}}\left[1-{{2}\over{\pi}}\arcsin\left({{r_{v}}\over{r_{v}+d_{\rm gv}}}\right)\right].\eqno{\hbox{(10)}}$$

$Z_{a}$, $Z_{v}$, and $Z_{g1-3}$ that denote the constriction effects are calculated based a conformal mapping approach. The conformal mapping approach was used for 2-D thin film patterns in [12] and [13], whereas recent research has shown its potential in 3-D substrate resistances [14]. Fig. 5(a) shows the cross-sectional view of two back-to-back connected contacts (C–D and ${\rm C}^{\prime}{-}{\rm D}^{\prime}$) in complex plane $z$. The resistance between the two contacts cannot be easily derived because simple closed-form expressions for the current flow lines (dashed lines with arrows) or the equipotential surfaces (dot lines) at the near field are usually unavailable (such as the case in Fig. 1). Using conformal mapping, the contacts in the $z$-plane can be mapped to a $z1$-plane, where the structure is, however, simple and the resistance can be derived. Because the mapping is conformal, the current flow and equipotential surface are kept perpendicular at any places. This guarantees that the resistance between the contacts in the $z1$-plane is the same as that in the $z$-plane. In the $z1$-plane, half of the resistance between the contacts is TeX Source $$R={{\rho}\over{t}}L_{1}/W_{1}\eqno{\hbox{(11)}}$$ where $\rho$ is the resistivity of the medium and $t$ is the thickness (perpendicular to this paper). $R$ can also be represented using the available parameters (layout/substrate parameters) in $z$-plane with a correction term TeX Source $$R={{\rho}\over{t}}[(1-Y)/X+L_{e}/XL]\eqno{\hbox{(12)}}$$ where $L_{e}$ is the equivalent length for correction of the neglected constriction resistance. It is clear that TeX Source $$L_{e}=XLL_{1}/W_{1}-(1-Y)L.\eqno{\hbox{(13)}}$$

In the case of $X\ll 1$, and $Y<0.5$, $L_{e}$ can be approximated as [12], [13] TeX Source $$L_{e}={{Y}\over{X}}-{{2}\over{\pi}}\ln{\left[\sinh\left({{Y\pi}\over{2X}}\right)\right]}\eqno{\hbox{(14)}}$$ and for the case of $X\ll 1$ and $Y>0.5$, $L_{e}$ can be approximated as [13] TeX Source $$L_{e}=K(p)/K^{\prime}(p)-(1-Y)K(k)/K^{\prime}(k)\eqno{\hbox{(15)}}$$ where $p=\tanh [{\pi (1-Y)}/{2X}]$. $K$ is the complete elliptic integral of first kind and $K^{\prime}(k)=K(\sqrt{1-k^{2}})$.

Given that $R_{p2}$ and $R_{p3}$ are the lateral constriction resistances of the contact [Fig. 5(b)], they can be easily calculated by extending the lateral length by $L_{e}$. $R_{p1}$ represents the resistance between the inner two dashed lines beneath the contact. For circular aggressor and victim, the inner dashed lines represent the same equipotential surface around the contact and thus $R_{p1}=0$. Thus, the value for $R_{a}$ in Fig. 2 can be found by TeX Source $$\eqalignno{R_{a}=&\,{{1}\over{2\pi{G}}}{{\rm acosh}\,\left[{{1}\over{2}}\left({{(D+L_{\rm ea})^{2}}\over{r_{a}r_{g}}}-{{r_{a}}\over{r_{g}}}-{{r_{g}}\over{r_{a}}}\right)\right]}\cr &-{{1}\over{2\pi{G}}}{{\rm acosh}\,\left[{{1}\over{2}}\left({{D^{2}}\over{r_{a}r_{g}}}-{{r_{a}}\over{r_{g}}}-{{r_{g}}\over{r_{a}}}\right)\right]}&{\hbox{(16)}}}$$ where $L_{\rm ea}$ is the equivalent length for calculating the constriction resistances of the aggressor. Similarly TeX Source $$R_{v}={{1}\over{2\pi{G}}}{\ln{{r_{v}+L_{\rm ev}}\over{r_{v}}}}\eqno{\hbox{(17)}}$$ where $L_{\rm ev}$ is the equivalent length for calculating the constriction resistances of the victim. For guard rings, the inner dashed lines are not necessarily on the same equipotential surface as they are at the side facing the aggressor and victim, respectively. Hence $R_{p1}$ is not necessarily zero and it can be calculated by TeX Source $$R_{p1}={{1}\over{2\pi{G}}}\ln{{r_{g}}\over{r_{\rm gin}}}.\eqno{\hbox{(18)}}$$

Assuming $R_{p2}$ of the guard ring is at the aggressor side, then it can be calculated by TeX Source $$R_{p2}={{1}\over{2\pi{G}}}\ln{{r_{g}+L_{\rm eag}}\over{r_{g}}}\eqno{\hbox{(19)}}$$ where $L_{\rm eag}$ is the equivalent length of the constriction resistance. $R_{p3}$ is the lateral resistance of a ring with inner radius of $r_{\rm gin}-L_{\rm egv}$ and outer radius of $r_{\rm gin}$ TeX Source $$R_{p3}={{1}\over{2\pi{G}}}\ln{{r_{\rm gin}}\over{r_{\rm gin}-L_{\rm egv}}}\eqno{\hbox{(20)}}$$ where $L_{\rm egv}$ is the equivalent length of the constriction resistance at the victim side. The $\Pi$ network in Fig. 5(b) is transferred to a Y-network to obtain $R_{g1-g3}$: $R_{g1}={R_{p2}R_{p3}}/{(R_{p1}+R_{p2}+R_{p3})}$, $R_{g2}={R_{p2}R_{p1}}/ {(R_{p1}\!+\! R_{p2}\!+\! R_{p3})}$, $R_{g3}\!=\!{R_{p3}R_{p1}}/{(R_{p1}\!+\!R_{p2}\!+\!R_{p3})}$.

SECTION III

The proposed model is based on the approximation of horizontal current flow in the P-well layer, which is valid for thin P-wells but less so for thicker P-wells. EM simulation has been done to validate the model and to illustrate the applicable range of the model in processes with different P-well resistivity and thickness. The schematic in Fig. 1 and EM simulation software CST STUDIO SUITE were used for the simulation. To simplify the simulation uniform conductivity is used for the P-well layer because nonuniform conductivity profile cannot be defined in the EM simulator. Fig. 6(a) and (b)show the calculated and simulated $R_{\rm gv}$ and $R_{\rm ag}$, respectively. Here, $R_{\rm ag}=R_{a}+R_{g1}+(R_{\rm aw}+R_{g2})//(R_{\rm as}+R_{\rm gs})$, and $R_{\rm gv}=R_{v}+R_{g1}+(R_{\rm vw}+R_{g3})//R_{\rm vs}$. It can be seen that the calculated resistances match the simulated results well, especially for small thicknesses (error ${<}{5\%}$ for $t_{1}<5 \mu{\rm m}$). As most CMOS processes fall within this range the proposed model is widely applicable.

SECTION IV

Fig. 7(a) shows the guard ring testing fixtures (denoted by A-L) that have been fabricated using a standard 0.18 $\mu{\rm m}$ 6-metal CMOS process to verify the proposed model. The process is aluminum and silicon dioxide-based and the process parameters are given in Fig. 7. The value for $G$ is calculated using (6) based on the ion implantation profile of the process.

The reference fixture M has no guard ring and the circuit model for it is a two-port network (port $g$ is removed and so the components related to guard ring.). The calculation of remaining impedance components are the same as the calculation in fixtures A-L except that $R_{\rm vw}$ is calculated using the same (5) as $R_{\rm aw}$ instead of (7) [14]. Fixtures O and P are the open and short fixtures for deembedding. Fixture O has the same layout as fixtures A-L except that the guard ring, the aggressor contact, the victim contact, and their connections to the top metal are removed (Metal-6 straps are kept). Fixture P has the same layout as O but with signal pads connected to the GND pads on the top metal layer. The side length of all the aggressor and victim contacts was chosen to 20 $\mu{\rm m}$.

Ground-Signal-Ground (G-S-G) pads are used for on-wafer resistance and S-parameter measurements. An example fixture and the simplified three-port model of Fig. 2 are shown in Fig. 7(b). The aggressor and victim contacts are connected to the signal pads using vias and metal1–6 [Fig. 7(c)]. The ${\rm P}^{+}$ guard ring is connected to metal-1, and then connected to the top metal layer, metal-6 using vias at point $C$. A strap on metal-6 is connecting point $C$ to the reference GND (point GND). Due to the nonzero resistivity the metal straps add on more impedance in the path from the guard ring to GND, which cannot be deembedded. As shown in Fig. 7(b), an impedance $Z_{\rm gg}$ is used to include this effect into the equivalent circuit of the guard ring as $Z_{\rm gg}=R_{\rm gg}+j\omega{L_{\rm gg}}=R_{\rm ring}+R_{\rm st}+j\omega{L_{l1}}+j\omega{L_{l2}}$, where $R_{\rm ring}$ is the resistance between points $A$ and $C$. Two metal-1 straps A-C, and A-B-C are connected in parallel. $R_{\rm ring}$ can be calculated based on the resistance of each strap using their lengths and sheet resistivity of metal-1. $R_{\rm st}$ is the resistance of the strap connecting the guard ring and the GND. $L_{l1}$ and $L_{l2}$ are the inductance of the straps C-D and D-GND, respectively. $R_{\rm st}$ is calculated in the similar way as $R_{\rm ring}$ but using the sheet resistivity of metal-6. $L_{l1,2}$ (in nH) are given by the equation of the self inductance for a $l$-meter long strap [15] as follows: TeX Source $$L_{l}={{l}\over{5}}\left[\ln{\left({{2\cdot l}\over{(w+t)}}\right)+{{0.223(w+t)}\over{l}}}+0.5\right]\eqno{\hbox{(21)}}$$ where $w$ and $t$ are the width and thickness of the metal strap C-D and D-GND, respectively.

In the verification. $R_{\rm ag}$ and $R_{\rm gv}$ and $R_{\rm av}$ are used to represent the resistance between point ${\rm S}_{1}$-GND, ${\rm S}_{2}$-GND, and ${\rm S}_{1}-{\rm S}_{2}$, respectively. Hence, $R_{\rm ag}=R_{a}+R_{g1}+(R_{\rm aw}+R_{g2})// (R_{\rm as}+R_{\rm gs})+R_{\rm gg}$, $R_{\rm gv}=R_{v}+R_{g1}+(R_{\rm vw}+R_{g3})//R_{\rm vs}+R_{\rm gg}$, and $R_{\rm av}\!=\!R_{a}\!+\!R_{v}\!+\!(R_{\rm vw}\!+\!R_{g3})//R_{\rm vs}\!+\!(R_{\rm aw}\!+\!R_{g2})//(R_{\rm as}+R_{\rm gs})$. Further, the sum $R_{g1}+R_{\rm gg}$, has been extracted from the measured results using $R_{g1}+R_{\rm gg}={(R_{\rm ag}+R_{\rm gv}-R_{\rm av})}/{2}$.

The measured and calculated $R_{\rm ag}$ and $R_{\rm gv}$ of guard ring fixtures with varying $d_{\rm gv}$ are shown in Fig. 8(a). It can be seen that the calculated results match the measured results very well. It should be noted that $R_{\rm gv}$ is still about 20 $\Omega$ even when the guard ring is very close to the victim contact $(d_{\rm gv}\>=\>0.28 {\mu}{\rm m})$. In this case, the constriction resistances at the near field of the victim and guard ring $(R_{g1},R_{v})$ dominate the value of $R_{\rm gv}$.

The measured and calculated $R_{\rm ag}$ and $R_{\rm gv}$ of guard ring fixtures with varying $d_{\rm ag}$ are shown in Fig. 8(b). It can be seen that the measured and calculated $R_{\rm gv}$ is almost constant. This is because only $d_{\rm ag}$ is varying but not the guard ring layout in this test. It can also be seen that $R_{\rm ag}$ increases as $d_{\rm ag}$ is increasing. In addition, a saturation effect can be observed for longer distances.

Guard ring fixtures with varying $w_{g}$ and fixed aggressor-to-victim distance are also investigated. The measured and calculated $R_{\rm ag}$ and $R_{\rm gv}$ are shown in Fig. 8(c). It can be seen that $R_{\rm ag}$ decreases as the guard ring widens and approaches the aggressor. $R_{\rm gv}$ is almost constant for most of the width values. This is because the charge distribution is mainly at the edge of the contact. Thus, the guard ring spreading resistance is close to the resistance of a circular contact with the same radius [11]. When $w_{g}$ is close to zero, both $R_{\rm ag}$ and $R_{\rm gv}$ increase drastically because of the significantly increased constriction resistance of the guard ring $(R_{g1})$. When $w_{g}=0$, which is the case of no guard ring (fixture M), $R_{g1}=\infty$, and $R_{g2}=R_{g3}=0$. In this scenario, there is no resistive coupling between port $a$ and port $g$.

Another investigation focuses on guard rings with varied $w_{g}$ and fixed $d_{\rm ag}$ and $d_{\rm gv}$. Results show that both $R_{\rm ag}$ and $R_{\rm gv}$ are almost constant when the width of the guard ring is increasing [Fig. 8(d)]. This is because the near field constriction resistance is dominating the total values of $R_{\rm ag}$ and $R_{\rm gv}$ for the fixtures in this test. Similar to the case in Fig. 8(c), $R_{\rm ag}$ and $R_{\rm gv}$ increase remarkably when the width of the guard ring is close to zero.

The proposed model has been verified by S-parameter measurements. Fig. 9(a) shows the measured and calculated $\vert{\rm S}_{21}\vert{\rm s}$ of the reference fixture and guard rings with varying guard ring width. Good match between the modeled and the measured results is shown. In addition, stronger coupling in the guard ring fixtures is observed at higher frequencies. This is mainly because of $L_{\rm gg}$ [Fig. 7(b)] and parasitical capacitances between the aggressor, guard ring, and victims. A decreased coupling in the reference fixture is observed at higher frequencies. This is mainly because of the aggressor-to-GND and victim-to-GND capacitances [16]. It can be seen that the noise suppression level decreases drastically when the guard ring is wide and close to the aggressor. This indicates that a wide guard ring may lead to deteriorations of the noise suppression performance.

Fig. 9(b) shows the measured and calculated $\vert{\rm S}_{21}\vert{\rm s}$ of guard rings with varying guard ring-to-victim distances. Apart from the good agreement between the measured and calculated results, it can also be seen that the coupling strength increases when the distance between the guard ring and victim increases. This indicates that the guard ring should be placed close to the victim to achieve a better suppression of the substrate noise when the distance between aggressor and victim is fixed.

Fig. 9(c) shows the measured and calculated $\vert{\rm S}_{21}\vert{\rm s}$ of guard ring fixtures with varying aggressor-to-guard ring distances. A clear enhancement of the noise suppression level can be obtained as $d_{\rm ag}$ is increasing. But, the enhancement is saturated for longer distances, which is consistent with the results in Fig. 8(b).

The measured and calculated S-parameters of guard rings with varying $W_{g}$ and fixed $d_{\rm ag}$ and $d_{\rm gv}$ are shown in Fig. 9(d). It can be seen that the suppression levels of the fixtures are close to each other even though the guard ring widths are drastically different. This feature is accurately predicted by the calculated results based on the proposed model. This indicates that increasing the guard ring width cannot guarantee an improved noise suppression performance.

As shown in Fig. 9, the predicted S-parameters well match the experimental results in a broad frequency band ranging from 45 MHz to 10 GHz. Therefore, the proposed model is of interest not only for narrow-band mixed-signal ICs, in which the interested noise frequency band is usually at a few hundred MHz [17], but also for broad band systems such as UWB ICs [18]. In addition, the proposed model reveals the area effectivenesses of different guard ring designs. Here, an area effectiveness factor is defined by Area/Iso, where Area is calculated by multiplying the length and width of the guard ring fixture and Iso is the measured $\vert{\rm S}_{21}\vert$ at 100 MHz of each guard ring fixture. A small area effectiveness value indicates a chip area-saving design. As shown in Table I, the guard ring with small $w_{g}$ and small $d_{\rm gv}$ (fixture C and D) provides the best area effectiveness among all the fixtures. When $d_{\rm ag}$ increases (fixture I), the area effectiveness drops, but is still better than other fixtures. Based on the proposed model design guidelines for area-efficient ${\rm P}^{+}$ guard rings can be concluded as follows.

- Determine $w_{g}$. Guard ring widths of a few $\mu{\rm m}$, e.g., 5 $\mu{\rm m}$, should be appropriate for most cases.
- Determine $d_{\rm gv}$. The guard ring should be placed close to the victim. The minimum ${\rm P}^{+}\hbox{-}{\rm P}^{+}$ distance in layout design constrain could be used.
- Determine $d_{\rm ag}$. $d_{\rm ag}$ should be less than the side length of the contacts, as the enhancement in noise suppression saturates for large $d_{\rm ag}$ values.
- S-parameter calculation. The components in the model can be calculated using (2) to (20) with the designed parameters. Then the S-parameters can be calculated using SPICE simulations.

For designs aiming at optimum noise suppression level instead of layout area efficiency, the design guidelines for $w_{g}$ and $d_{\rm gv}$ are still applicable. But $d_{\rm ag}$ should be as large as possible [Fig. 9(c)]. Besides, the guard ring should always be well connected to the closest GND to minimize $Z_{\rm gg}=R_{\rm gg}+jwL_{\rm gg}$ in practical designs. It can help to maximize the noise suppression performance and improve the performance at higher frequencies. It is, however, difficult to achieve a zero $Z_{\rm gg}$ because of the nonzero resistivity of interconnects. Using the proposed model achievable values of $Z_{\rm gg}$ can be included in the calculation, which is useful to obtain more accurate predictions of the noise suppression performance.

SECTION V

This paper presents a compact ${\rm P}^{+}$ guard ring model for substrate noise analysis. Different from existing compact models, the proposed model can handle ${\rm P}^{+}$ guard rings implemented using lightly doped CMOS substrates with a P-well layer. The model is scalable to guard ring parameters and requires no fitting factors. Based on the proposed model, the substrate noise suppression performance of ${\rm P}^{+}$ guard rings in terms of S-parameters can be efficiently predicted in a broad frequency band up to at least 10 GHz. The model has been validated by EM simulations and experimental measurements using a standard 0.18-$\mu{\rm m}$ CMOS process. In addition, design guidelines of ${\rm P}^{+}$ guard rings have been provided to miniaturize the chip area occupied by guard rings, while maintaining a desired noise suppression level. The approach used to obtain the model of ${\rm P}^{+}$ guard rings in this paper can also be helpful for other guard ring designs such as ${\rm N}^{+}$ guard rings.

This work was supported by the Danish Research Council for Technology and Production Sciences. The review of this paper was arranged by Editor M. Darwish.

M. Shen, J. H. Mikkelsen, O. K. Jensen, and T. Larsen are with the Technology Platforms Section, Department of Electronic Systems, Aalborg University, Aalborg 9220, Denmark (e-mail: mish@es.aau.dk; jhm@es.aau.dk; okj@es.aau.dk; tl@es.aau.dk).

K. Zhang and T. Tian are with the Shanghai Institute of Microsystem and Information Technology, Shanghai 200050, China (e-mail: kezhang@mail.sim.ac.cn; tiantong@mail.sim.ac.cn).

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