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Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design

Figure 1

Figure 1
(a) Characterizing the memristor and (b) change of resistance when a 3.6 V p–p square wave is applied.

Figure 2

Figure 2
(a) Three transistor–two memristor SRAM cell (b) circuit when Formula${\rm RD}={0}$, Formula${\rm WR}={1}$, and Formula${\rm Comb}={1}$. (c) Circuit when Formula${\rm RD}={1}$, Formula${\rm WR}={0}$, and Formula${\rm Comb}={1}$.

Figure 3

Figure 3
16×16 array structure.

Figure 4

Figure 4
(a) Timing diagram of input pulses during write operation. (b) Change of resistance of the two memristors of cell20 during write operation.

Figure 5

Figure 5
Timing diagram of read operation.

Figure 6

Figure 6
Evidence of non-volatility of the memristor SRAM cell. After writing “1” in cell 18, all the power sources are turned off during the time interval 50–69 ns. A read operation is done after turning on the power sources and found “1” in cell 18.

Figure 7

Figure 7
Inverse relation between mobility of the memristor and the write cycle time.

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