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TUNNELING field-effect transistor (TFET) have garnered interests by its virtues of reduced short-channel effects (SCEs), steep subthreshold slope, and low power consumption [1], [2]. In order to overcome the low off-state current Formula$(I_{\rm{off}})$ of a silicon (Si) TFET, efforts have been made to improve its performance with regard to novel structuring and materials [3], [4], [5], [6], [7]. The performances of circuits embedding TFETs have been reported with increasing popularity in both direct-current (DC) and radio-frequency (RF) aspects [8], [9], [10], [11]. In this study, a germanium (Ge)/gallium arsenide (GaAs) heterojunction TFET with a nanowire channel is evaluated for circuit application by device simulation [12]. Although good device-level performance metrics do not always translate into a significant advantage at the circuit level, any improvement in circuit performances are expected by development and good designing of device-level components.

Drive current Formula$(I_{\rm{on}})$ is greatly improved by the narrow energy bandgap of Ge (0.66 eV) and the ambipolar behavior due to gate-induced drain leakage (GIDL) is effectively suppressed by the wide energy bandgap of GaAs (1.42 eV) [7]. Formula$I_{\rm{on}}$ of TFET is mainly determined by energy bandgap Formula$(E_{\rm{G}})$ of source material and effective tunneling mass of carriers [13], [14], [15]. A steeper slope is expected by BTB tunneling in TFET operations than by drift-diffusion transports in conventional MOSFETs. Moreover, the small swing is highly guaranteed by grafting Ge with a narrow energy-bandgap at source and GaAs with a large one at drain [7]. This makes it difficult to accurately match the currents of p- and n-type TFETs in a complementary metal-oxide-semiconductor (CMOS) configuration, unlike the conventional CMOS circuit where the currents are simply matched by scaling the widths in consideration of the ratio of electron and hole mobilities. Also, scaling the perimeter of nanowire for inverter current matching can be challenging from a fabrication process view. Thus, in this work, we are more interested in application of Ge/GaAs heterojunction TFET for analog circuits where single-type transistors can be adopted rather than digital applications. Fig. 1(a) and (b) show the schematics of Ge/GaAs heterojunction TFET and common-source (CS) amplifier adopting it. Besides the genuine merits for enhanced performances in TFET operations, another reason is found in a fact that it is very probable to achieve integrated optoelectronics through this material system [16]. Also, a recent study supports the Ge and Formula${\rm Al_{1-x}}{\rm GaxAs}$ system has a strong potential for III-V on group-IV heterogeneous integrated circuits (ICs) owing to its reliable interface morphology [17]. In the device schematic shown in Fig. 1(a), the doping concentrations of the p-type source and n-type drain (intrinsic channel) were Formula$1\times 10^{20} {\rm{cm}}^{-3}$ and Formula$1.1\times 10^{18} {\rm{cm}}^{-3}$, respectively. A high p-type doping concentration reaching Formula$10^{20} {\rm{cm}}^{-3}$ can be achieved by ion implantation and rapid thermal annealing (RTA) [18]. The nanowire channel radius, channel length, and gate oxide thickness were 10 nm, 30 nm, and 2 nm. Metal contact (Au) was used at each terminal to take the effect of contact resistance into account. Considering that the materials are epitaxially grown in the upward direction from the substrate (if no particular initial structure is preferred), it should be a way avoiding complicated fabrication processes to construct vertical nanowire channel. After the material growth, processing flows employed in the previous researches may follow [19], [20], [21]. Fig. 1(b) illustrates the simulated circuit configuration.

Figure 1
Fig. 1. Schematics of the simulated device and circuit. (a) Nanowire Ge/GaAs heterojunction TFET. (b) CS amplifier configuration with the TFET device.


Mixed-mode simulation is useful when a newly developed device without explicitly known direct-current (DC) and alternating-current (AC) parameters is required as a component in the circuit simulation. In a commercial circuit simulation tool, a set of DC and AC parameters can be simply entered for an electron device of which current equation and necessary parameters are well known and lumped into a macro-model. However, the current equation of TFET operated not by drift-diffusion mechanism but by BTB tunneling has not been fully developed for circuit simulations. Thus, monitoring the device-circuit interaction by mixed-mode simulation is made possible on the basis of real-time charge behaviors. A circuit simulator embedded in the device simulator calculates node voltages at given bias in the whole circuit, and in response to the input values of voltages at each terminal of the core device, the device simulator returns terminal currents to the circuit. The device simulation is performed by a number of physical models not by already known parameters. The recursive interactions between device and circuit (device simulation and embedded circuit simulation) eventually provide all the node voltages and currents at an operating point (Formula$Q$-point) of interest. For the device simulation multiple models were accompanied for higher accuracy: concentration-dependent mobility model, Shockley-Read-Hall recombination model, bandgap narrowing model, and non-local BTB tunneling calculation. Due to a limitation in current-version capability of the tool used in this work, the non-local calculation is only activated for a 2-dimensional (2-D) device simulation. We first designed the nanowire Ge/GaAs heterojunction TFET in the 2-D plane, rotated it about the cylindrical symmetry axis, and carried out the simulations to obtain more reliable results as if the device had had a 3-D structure. This pseudo 3-D simulation results are generated from a discrete device and fed back into the circuit simulation repeatedly.

Poles and zeroes were extracted from the frequency response represented by Bode plots obtained by the mixed-mode simulation results. MATLAB coding was performed in conjunction to establish the simplest transfer function by iteratively matching the voltage gains from simulation and modeling results with the least discrepancy. From a system view, transfer function of a circuit block makes it easier to cascade a number of functional blocks for constructing a higher-level circuit. Also, transfer function would provide another way to validate the passive elements extracted from a nanoscale radio-frequency (RF) device by mathematical formulations [22], [23].



Fig. 2(a) shows the transfer Formula$(I_{\rm{D}}\hbox{-}V_{\rm{GS}})$ and output Formula$(I_{\rm{D}}\hbox{-}V_{\rm{DS}})$ curves of a designed Ge/GaAs heterojunction TFET device. Drain currents Formula$(I_{\rm{D}})$ were normalized by the channel width. The subthreshold swing Formula$(S)$ was extracted to be the reciprocal of maximum instantaneous slope of tangential lines on the plot. Formula$S$ values were 23.6 mV/dec and 31.6 mV/dec at drain voltages Formula$(V_{\rm{DS}})$ of 50 mV and 1 V, respectively. Fig. 2(b) depicts the DC transfer curve Formula$(V_{\rm{IN}}\hbox{-}V_{\rm{OUT}})$ of the CS amplifier based on the nanowire Ge/GaAs heterojunction TFET. The operating voltage in this work is not a unique solution to operate the suggested TFET and its circuit. However, the set of operating voltages were precisely determined so that the highest linearity in small-signal operation and a wide swing window could be secured Formula$(V_{\rm{OUT}}=0 {\rm V})$ when a split-source of Formula$\pm V_{\rm{DD}}=\pm{1} {\rm V}$ was applied to the circuit as confirmed in Fig. 1(b). The source resistance Formula$(R_{{1}})$ was set to 50 Formula$\Omega$, and Formula$R_{{2}}=4 {\rm k}\Omega$ was used at the drain terminal to obtain a proper Formula$Q$-point providing a full symmetric swing about the Formula$V_{\rm{OUT}}=0 {\rm V}$ in Fig. 2(b). The maximum slope of the Formula$V_{\rm{IN}}\hbox{-}V_{\rm{OUT}}$ curve was Formula$[dV_{\rm{OUT}}/dV_{\rm{IN}}]_{\rm Max}=-3.65 {\rm V}/{\rm V}$ at Formula$V_{\rm{IN}}=0.48 {\rm V}$, and the actual location of swing center was at Formula$V_{\rm{IN}}=0.53 {\rm V}$. The difference in these two Formula$V_{\rm{IN}}$ values is not significantly large as to distort the amplification of a small signal with an amplitude of 10 mV, and thus, Formula$V_{\rm{IN}}=0.53 {\rm V}$ was used as the gate bias Formula$(V_{\rm{GS}})$ throughout the simulations.

Figure 2
Fig. 2. DC characteristics. (a) Transfer Formula$(I_{\rm{D}}\hbox{-}V_{\rm{GS}})$ and output Formula$(I_{\rm{D}}\hbox{-}V_{\rm{DS}})$ curves of a device at different bias conditions. (b) DC transfer curve Formula$(V_{\rm{IN}}\hbox{-}V_{\rm{OUT}})$ of the CS amplifier.

Fig. 3(a) and (b) depict the frequency responses of the designed CS in Bode plot, the magnitude gain and phase shift, respectively. The small-signal amplitude Formula$(v_{\rm{in}})$ was 10 mV: Formula TeX Source $$v_{in}(t)\;=\; 10\sin \omega t\;=\; 10\sin 2\pi ft{\rm\; (mV)}\eqno{\hbox{(1)}}$$

Figure 3
Fig. 3. Frequency response. (a) Magnitude gain and (b) phase shift. The line and circles indicate the mixed-mode simulation and modeling results, respectively.

As can be assured by Fig. 3(a), the configured circuit functions as a low-pass filter (LPF) and its low-frequency voltage gain was 10.73 dB (3.44 V/V). The 3-dB roll-off Formula$(f_{{-3{\rm dB}}})$ and the unity-gain frequencies were 320 GHz and 2 THz, respectively. It is predicted that the system can be described by a transfer function with one zero and two poles: Formula$z_{{1}}=1.27\times{10^{12}} {\rm Hz}$, Formula$p_{1}=3.20\times 10^{11} {\rm Hz}$, and Formula$p_{\rm{2}}=2.39\times 10^{13} {\rm Hz}$. As can be confirmed by Fig. 3(b), the phase difference shows consecutive three times of Formula${-}{90}^{\circ}$ shifts Formula$(180^{\circ}-3\times 90^{\circ}=-90^{\circ})$. The only possible combination of type and sign assignments to the characteristic solutions in order to achieve a monotonic phase shift of Formula${-}{270}^{\circ}$ is one right-half-plane (RHP) zero and two left-half-plane (LHP) poles. Consequently, the simplest transfer function for the single-zero two-poly (SZTP) is modeled as follows: Formula TeX Source $$H(s)=A{{s-z_{1}}\over{(s+p_{1})(s+p_{2})}}={{1.3\times 10^{14}(s-8\times10^{12})}\over{(s+2.01\times 10^{12})(s+1.5\times 10^{14})}}\eqno{\hbox{(2)}}$$

The open circles in Fig. 3(a) and (b) are the results from MATLAB coding with the modeled transfer function in (2).

Also, the filled circle and crosses in Fig. 3(a) shows the frequency locations of one zero and two poles extracted from (2). The frequency extrapolated from the first-pole roll-off is 1 THz as shown in Fig. 3(a), which is more relevant for circuit performance than 2 THz where the mathematical unity gain is obtained.

Besides the voltage amplification, current and unilateral power gains are depicted as a function of frequency to obtain another set of practical RF parameters, as shown in Fig. 4(a). Maximum cutoff frequency Formula$({f_{\rm{T}}})$ and maximum oscillation frequency Formula$(f_{\rm{max}})$ extracted by extrapolation above 600 GHz were 5.52 THz and 10.4 THz, respectively. In the analog or mixed-signal circuits, the linearity of CMOS is essential. Third-order intercept (IP3) is one of the indices of linearity and higher IP3 value is desirable [24]. In order to achieve a high IP3, high first-order harmonic value Formula$(g_{\rm{m}})$ and 3rd-order harmonic value Formula$(g_{\rm{m}}3=g_{\rm{m}}^{\prime\prime})$ are necessary as can be implied by the mathematical definition of IP3 in (3). Fig. 4(b)shows the extracted IP3 as a function of gate-to-source voltage Formula$(V_{\rm{GS}})$ at Formula$V_{\rm{DS}}=1.0 {\rm V}$. Formula TeX Source $${\rm IP}3=10\log\left({g_{m}}\over{g_{m}^{\prime\prime}}\right)+12.2{\rm\; [dBm]}\eqno{\hbox{(3)}}$$

Figure 4
Fig. 4. Evaluation of RF parameters and linearity. (a) Current and unilateral power gains. (b) IP3 as a function of gate-to-source voltage Formula$(V_{\rm{GS}}) (V_{\rm{DS}}=1.0 {\rm V})$.

It is confirmed from Fig. 4(b) that high linearity is secured for most of operating voltage Formula$(V_{\rm{GS}})$ near and above Formula$V_{\rm{GS}}=1.0 {\rm V}$. Considering the simulated RF performances, remote gas sensing, electronic components for THz-spectroscopy, and high-speed integrated optoelectronic systems would be the applications of the Ge/GaAs heterojunction TFETs [25], [26], [27].



The DC and AC performances of a CS amplifier adopting the nanowire Ge/GaAs heterojunction TFET were evaluated by device and mixed-mode circuit simulations. Its cut-off and unity-gain frequencies were 320 GHz and 2 THz, respectively. Furthermore, the transfer function of the simplest form was successfully modeled and verified by MATLAB programming. It is convinced that the nanowire Ge/GaAs heterojunction TFET has a strong potential for wide variety of applications to high-speed integrated circuits.


This work was supported in part by the Center for Integrated Smart Sensors funded by the Korean Ministry of Education, Science, and Technology as the Global Frontier Project(CISS-2012M3A6A6054186) and in part by the Kyungpook National University Research Fund, 2012. The review of this paper was arranged by Editor C. McAndrew.

S. Cho and J. S. Harris, Jr. are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail:;

H. Kim and B.-G. Park are with the Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea (e-mail:;

H. Jhon is with the System LSI Division, Samsung Electronics Company, Ltd., Yongin City, Gyeonggi-Do 446-711, Korea (e-mail:

I. M. Kang is with the School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea (e-mail:

Color versions of one or more of the figures in this paper are available online at


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Seongjae Cho

Seongjae Cho

Seongjae Cho (S'07–M'10) received the B.S. and Ph.D. degrees in electrical engineering from the Department of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2004 and 2010, respectively.

He was a Teaching Assistant for semiconductor process education at the Inter-University Semiconductor Research Center, SNU, from 2005 to 2007. Also, he was with the National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan, with the co-support from the Korea Science and Engineering Foundation and the Japan International Science and Technology Exchange Center for researching silicon nanoscale CMOS devices. From March 2010 to September 2010, he was a Post-Doctoral Researcher with EECS, SNU, and since October 2010, he has been working with the Department of Electrical Engineering, Stanford University, Stanford, CA, USA. He has authored and co-authored more than 160 technical papers at journals and conferences. He currently holds eight Korean and U.S. patents. His current research interests include nanoscale CMOS devices, emerging memory devices, optoelectronic devices for optical interconnect, and integrated systems. Dr. Cho is a member of the IEEE Electron Device Society and IEEE Photonics, a Lifetime Member of the Institute of Electronics Engineers of Korea (IEEK), a member of the Institute of Electronics, Information and Communication Engineers, Optical Society of America, the International Society for Optics and Photonics. He was a recipient of the Distinguished Research Achievement Award from EECS, SNU, in 2009 and 2010, the Doyeon Paper Award from ISRC, SNU, in 2010, the National Research Foundation of Korea Fellowship in 2011, and the Haedong Young Engineer Award from IEEK in 2011.

Hyungjin Kim

Hyungjin Kim

Hyungjin Kim (S'10) was born in Busan, Korea, in 1988. He received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 2010 and 2012, where he is currently pursuing the Ph.D. degree in electrical engineering.

His current research interests include nanoscale silicon devices, tunneling field-effect transistors, and synapse-like devices for neuromorphic systems.

Heesauk Jhon

Heesauk Jhon

Heesauk Jhon (S'08) received the B.S. and M.S. degrees in electronics engineering from Kwangwoon University and Yonsei University, Seoul, Korea, in 2001 and 2004, respectively, and the Ph.D. degree in electrical engineering from Seoul National University, Seoul, in 2001. Since 2010, he has been a Senior Engineer at Samsung Electronics for high-power and mixed-signal IC designs. His current research interests include switching converter design, extremely low-cost and low-power RFICs design, and modeling of silicon-based active/passive devices.

Dr. Jhon received the Best Paper Award at the IEEE Student Paper Contest at the Seoul Section of Region 10 in 2008 and was listed in Marquis Who's Who in the World in 2010.

In Man Kang

In Man Kang

In Man Kang (M'11) was born in Daegu, Korea, in 1977. He received the B.S. degree in electronic and electrical engineering from the School of Electronics and Electrical Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D. degree in electrical engineering from the Department of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2007. He was a Teaching Assistant for semiconductor process education from 2001 to 2006 at the Inter-University Semiconductor Research Center (ISRC), SNU. From 2007 to 2010, he was a Senior Engineer at the Design Technology Team, Samsung Electronics Company, Ltd. In 2010, he joined KNU as a full-time Lecturer at the School of Electronics Engineering, where he is currently an Assistant Professor. His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistors, low-power nanoscale CMOS devices, GaN transistors, and light-emitting diodes.

Dr. Kang is a member of the Institute of Electronics and Engineers of Korea.

Byung-Gook Park

Byung-Gook Park

Byung-Gook Park (M'90) received the B.S. and M.S. degrees in electronic engineering from Seoul National University (SNU), Seoul, Korea, in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 1990.

From 1990 to 1993, he was with AT&T Bell Laboratories, where he contributed to the development of 0.1-Formula$\mu{\rm m}$ CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25-Formula$\mu{\rm m}$ CMOS. In 1994, he joined SNU as an Assistant Professor with the School of Electrical Engineering, where he is currently a Professor. In 2002 and 2010, he was with Stanford University, as a Visiting Professor. He led the Inter-University Semiconductor Research Center, SNU, as the Director from June 2008 to June 2010. He has authored and co-authored more than 930 research papers for journals and conferences and three books. He currently holds more than 100 Korean and U.S. patents. His current research interests include the design and fabrication of nanoscale CMOS, Flash memory devices, silicon quantum devices, and organic thin-film transistors.

Dr. Park has served as a Committee Member at several international conferences, including Microprocesses and Nanotechnology, IEEE International Electron Devices Meeting, International Conference on Solid State Devices and Materials, and Technical Program Chairs and General Chairs for the IEEE Silicon Nanoelectronics Workshop. In addition, he has been serving as an editor of IEEE Electron Device Letters. He is currently serving as an Executive Director of the Institute of Electronics Engineers of Korea (IEEK) and a Board Member of IEEE Seoul Section, Region 10. He was a recipient of the Best Teacher Award from SoEE in 1997, the Doyeon Award for Creative Research from ISRC in 2003, the Haedong Paper Award, and the Headong Academic Research Award from IEEK in 2005 and 2008, respectively, and the Educational Award from the College of Engineering, SNU, in 2006.

James S. Harris, Jr.

James S. Harris, Jr.

James S. Harris, Jr. (S'65–M'69–SM'78–F'88–LF'07) received the B.S., M.S., and Ph.D. degrees from Stanford University, Stanford, CA, in 1964, 1965, and 1969, respectively, all in electrical engineering.

In 1969, he joined the Rockwell International Science Center, Thousand Oaks, CA, USA, where he was one of the key contributors to ion implantation, molecular beam epitaxy, and heterojunction devices, leading to their preeminent position in GaAs technology. In 1980, he became the Director of the Optoelectronics Research Department. In 1982, he joined the Solid State Electronics Laboratory, Stanford University, as a Professor of electrical engineering, where he was the Director of the Solid State Electronics Laboratory from 1984 to 1998, the Director of the Joint Services Electronics Program from 1985 to 1999, and is currently the James and Ellenor Chesebrough Professor of electrical engineering, applied physics, and materials science in the Center for Integrated Systems. He has supervised more than 105 Ph.D. students, is the author or co-author of more than 850 publications, and holds 28 issued U.S. patents. His current research interests include the physics and application of ultrasmall structures and novel materials to new high-speed and optoelectronic devices and systems.

Dr. Harris is a member of the U.S. National Academy of Engineering and a fellow of the American Physical Society, the Optical Society of America, and the Materials Research Society. He was a recipient of the 2000 IEEE Morris N. Liebmann Memorial Award, the 2000 International Compound Semiconductor Conference Walker Medal, the IEEE Third Millennium Medal, an Alexander von Humboldt Senior Research Prize in 1998, and the 2008 International MBE Conference MBE Innovator Award for his contributions to compound semiconductor materials, devices, and technology.

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