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SECTION I

INTRODUCTION

THE unlicensed bandwidth between 57 and 66 GHz is released for broadband short-distance communications. As it is known, this is the widest portion of radio-frequency spectrum ever allocated in an exclusive way for wireless unlicensed application which allows multi-gigabit-per-second wireless communications [1], [2], [3], [4], [5], [6], [7]. Moreover, significant advancements in CMOS technology permit one to consider utilizing the 60 GHz band for high data rate applications including short range, wireless transmission.

There are already several standards for 60 GHz wireless communication, including IEEE 802.15.3c [8], IEEE 802.11ad [9], ECMA-387 [10], WirelessHD [11] and WiGig (Wireless Gigabit Alliance) [12]. Each is formed by a different community of potential users of technology. For example, IEEE802.11ad is one of standards for implementing WLAN computer communication for Gb/s speed utilizing 60 GHz frequency band, and WirelessHD and ECMA are developed to for streaming high-definition content between source and display devices. Most of the standards are focusing on very high speed communication (1–5 Gb/s) to enable wireless HDMI replacement.

Even though different standards are needed for different applications, an ability to operate across different standards is more preferable. These standards define 4 bands centered at 58.32 GHz/60.48 GHz/62.64 GHz/64.8 GHz, and ECMA-387 additionally defines channel-bonding bands centered at 59.4 GHz/61.56 GHz/63.72 GHz for higher data rates and more efficient constellations. In order to be compliant with these standards, mm-wave frequency synthesizers are required to generate each of these carrier frequencies. Moreover, as systems move away from single-carrier modulation and adopt more complex schemes, the design of mm-wave frequency synthesizers with quadrature output will become increasingly challenging.

Recently, for 60-GHz wireless communication system, the authors in [13] propose a 60 GHz PLL using a QVCO oscillating at the fundamental frequency. Another PLL with push-push VCO followed by a hybrid coupler [5] is published. In [14], a PLL with a sub-harmonic VCO which is used to inject a sub-harmonics quadrature Injection Locked Oscillator (ILO) [15], [16] is proposed. Among these publications, PLL using sub-harmonics quadrature ILO is preferred due to the best phase noise performance at 60 GHz. As shown in Fig. 1, a sub-harmonic injection-locked quadrature frequency synthesizer is used to generate these carrier frequencies for a direct-conversion TDD transceiver. However, due to inaccurate active/passive device modeling at mm-wave frequency band, it is difficult to guarantee the proper operation of the 60 GHz ILO, especially including PVT variations. The typical locking range of QILO is only several hundred MHz. As a result, a small shift of free-running frequency caused by PVT variations can lead the QILO unable to lock to the input signal. In addition, the undesired free-running frequency drift also causes considerable I/Q mismatch [14]. Therefore, a calibration scheme is needed to tune the free-running frequency of QILO for robustness of its operation and small I/Q mismatch in various conditions.

Figure 1
Fig. 1. Diagram of a 60 GHz direct conversion TDD transceiver using a sub-harmonic injection-locked quadrature frequency synthesizer.

A conventional calibration technique [13], [17], which is operated only at start-up, cannot track ILO frequency drift as temperature varies, thus, another method, which would automatically correct frequency drift by frequency feedback, is needed inevitably. In this paper, a 60 GHz frequency synthesizer with frequency calibration scheme [18] is proposed for millimeter-wave TDD transceivers. The proposed frequency synthesizer operates for a wide frequency range from 58.1 to 65.0 GHz, which supports all 60 GHz channels defined by the 60 GHz wireless communication standards. This paper is organized as follows. In Section II, a calibration scheme for a 60 GHz frequency synthesizer is introduced. The following section describes the circuit implementation in details. Section IV demonstrates experimental results of the proposed 60 GHz frequency synthesizer. Finally, a conclusion is summarized in Section V.

SECTION II

CALIBRATION SCHEME FOR 60 GHz SYNTHESIZER

A. Calibration Operation and Timing Between TDD Transceivers

A typical millimeter-wave TDD transceiver is composed of a transmitter (TX) and a receiver (RX) which has separate 60 GHz ILOs for their own operation as shown in Fig. 1. It is noted that the TX and the RX operate in different time slots, thus, the calibration of the 60 GHz ILO for the TX can be performed during RX time slots, and the calibration of the 60 GHz ILO for the RX can be performed during TX time slots. Fig. 2 shows the calibration operation and timing between TDD transceivers. If a transceiver A (TRX A) is transferring data stream to a transceiver B (TRX B), the data stream is divided into small packets. After the first packet is transmitted to the TRX B, an acknowledged packet will be transmitted from the TRX B back to the TRX A to confirm that the first packet was received successfully. The TRX A will wait until the acknowledged packet is received completely before starting to transfer the next packet. In this case, the most crucial part of timing that poses a time restriction for calibration occurs when an acknowledged packet is being sent and received from TRX B and TRX A respectively. Typically this length of time is composed of two shortest inter-frame spaces (SIFS) and one ACK packet length, which is limited to several Formula$\mu{\hbox {s}}$. For example, in IEEE 802.11ad, the SIFS length is 3 Formula$\mu{\hbox {s}}$ and ACK length including preamble is 1.2 Formula$\mu$ s, thus the maximum available duration for ILO calibration is limited to 7.2 Formula$\mu{\hbox {s}}$. Such a short interval imposes a strict requirement for the calibration time of the 60 GHz ILO. Fortunately, noted that TDD systems allow foreground calibration, it is feasible to calibrate the ILO frequency to the target frequency initially. Next, considering the fact that the ILO frequency drift caused by component aging and environmental changes is usually a gradual and slow process (compared to the time duration of Formula$\mu{\hbox {s}}$ level), a small frequency drift can be corrected easily within several calibration steps, which relaxes the severe requirement for the calibration time. Meanwhile, it is possible to monitor the frequency drift at regular intervals, which helps to reduce the overall power consumption.

Figure 2
Fig. 2. Calibration operation and timing between TDD transceivers.

B. Proposed Calibration Scheme

Fig. 3 shows a simplified diagram of the proposed synthesizer with the frequency calibration scheme. For the adoption of a down converting mixer, the 20 GHz PLL can be used as a reference for mixing 60 GHz output to lower frequency. However, directly mixing 20 GHz signal with 60 GHz signal is not feasible since the IF output frequency still requires a 40 GHz divider. Therefore, a better solution is to use a doubler or push-push amplifier to utilize the second harmonic of 20 GHz PLL to mix with the output of the ILO. Thereby, the output of mixer will be around 20 GHz where we can use dividers chain for further digital comparison.

Figure 3
Fig. 3. Conceptual diagram of the 60 GHz frequency synthesizer with the proposed frequency calibration scheme.

The process of calibration is carried out when the 20 GHz PLL is locked. At the initial state or during TX time slots, the ILO for RX outputs its free-running frequency, and the output of ILO for RX is down-converted to a frequency around 20 GHz by a mixer, through doubling of the 20 GHz PLL injection signal. After two separate divider chains, the frequency coming from the output of mixer and the 20 GHz PLL are compared using digital calibration circuits. The output of digital calibration circuit directly controls the digital code for a digital-to-analog converter, giving rise to adjust the ILO free running frequency. After several reference cycles, the 60 GHz ILO free-running frequency is close to 3 times the 20 GHz PLL output.

SECTION III

60 GHz SYNTHESIZER TOPOLOGY

The proposed 60 GHz frequency synthesizer mainly consists of a 20 GHz PLL, a 60 GHz quadrature ILO, a frequency down-converting circuit, and a digital calibration circuit. The block diagram of proposed 60 GHz synthesizer is depicted in Fig. 4.

Figure 4
Fig. 4. Block diagram of the proposed 60 GHz frequency synthesizer with frequency calibration.

A. 20 GHz PLL

The 20 GHz PLL consists of a phase-frequency detector (PFD), a current-steering charge pump, a 2nd-order on-chip low pass filter, an LC-VCO with a tuning range of 17.9-to-21.7 GHz, followed by a divide-by-2 CML divider, an divide-by-3 E-TSPC divider, a digital divide-by-5 divider, and a digital multi-modulus divider. The whole divide ratio can be controlled from 1620 to 1800 in steps of 30. This divide ratio combing with a 12 MHz frequency resulting from a halved off-chip 24 MHz reference enables synthesis of the required tones.

B. 60 GHz ILO

Figure 5
Fig. 5. Circuit schematic of the quadrature ILO.
Figure 6
Fig. 6. Circuit schematic of the variable capacitor part.

The circuit schematic of 60 GHz ILO is shown in Fig. 5. A quadrature 60 GHz LO signal can be obtained due to a quadrature I/Q configuration. The free-running frequency can be adjusted by a switched capacitor bank for coarse tuning, and a varactor which is controlled by the calibration circuit for fine tuning. The 20 GHz PLL signal is injected through the tail transistor of I oscillator. Fig. 6 shows the circuit schematic of the variable capacitor part, which consists of a MOS varactor providing continuous and fine tuning ability, and switched capacitor array allowing discrete and coarse tuning steps. By tuning QILO to be at the center of the locking range, the output I/Q mismatch can be minimized. However, as the free-running frequency of QILO shifts from being 3 times the injected frequency, a considerable I/Q mismatch will be occurred [14]. A simulated sensitivity of I/Q phase error as a function of control voltage of a varactor in the QILO is approximated to be 0.6 degree/mV [14]. This demonstrates the necessity of the ILO frequency calibration.

C. Down-Converting System

The down-converting system is composed of a frequency doubler, a mixer, and two notch filters. There are mainly two design considerations for the down-converting system. First of all, the occupied chip area should be minimized for low cost. Considering building blocks for the down-converting system are operated in the millimeter-wave regime, on-chip impedance match and inductive peaking are necessary to improve the gain and output power of active circuits. In this work, miniaturized transmission line and custom-designed inductors help to reduce the whole chip area. Secondly, a sufficient large output power is critical to driving the following divider stage. In this section, detailed circuit implementations together with their simulation results are introduced.

1) Frequency Doubler

The frequency doubler operates as a push-push amplifier which combines 2 phases with 180 degrees phase shift by combining output nodes. As a result, odd harmonics components are cancelled out and the second harmonic component survives. In this implementation, a simple differential amplifier is used as shown in Fig. 7, where output nodes are shorted. Even though the output signal is single-ended, it is enough to carry frequency information for calibration. In order to transfer maximum power to load, the input impedance of this frequency doubler is matched to the output impedance of 20 GHz PLL buffers at 50 Formula$\Omega$. This is done by the use of transmission line, and a custom-designed stacked inductor. The size of differential pair also affects the output amplitude. In this case, the width of transistors is chosen as Formula$2\times 20\ \mu{\hbox {m}}$. Another stacked inductor is utilized at the output node to peak at high frequency. Meanwhile, the transmission line is utilized to match output node to RF port of the next-stage mixer.

Figure 7
Fig. 7. Circuit schematic of the frequency doubler, along with other building blocks.
Figure 8
Fig. 8. Simulated output power of the frequency doubler.

With 0 dBm input power from 20 GHz PLL, the simulated output power of the frequency multiplier is shown in Fig. 8. The output power varies from about −9 dBm to −7 dBm over the output frequency range from 38.88 GHz to 43.2 GHz.

2) Mixer

Figure 9
Fig. 9. Circuit schematic of SSB mixer, along with other building blocks.

A double-balanced mixer is widely used due to its excellent port-to-port isolations while maintain reasonable conversion gain and noise performance. However, it requires differential RF inputs which would further complicate the topology of a frequency doubler or an additional Balun might be needed. In this work, the mixer is designed using a single-balanced topology which mixes the single-ended RF output from the frequency doubler at frequency around 40 GHz, with the differential LO output signal from the ILO at frequency around 60 GHz. The detailed schematic of the single-balanced mixer with other building circuits is shown in Fig. 9.

Figure 10
Fig. 10. Simulated conversion gain of the single-balanced mixer.

As mentioned earlier, a combination of stacked inductor at output node of the frequency doubler and transmission line is utilized to match the input impedance of RF port at the frequency of around 40 GHz. On the other hand, for matching the LO port, only transmission line is utilized since it is for higher frequency of 60 GHz. Another stacked inductor is used for the mixer core. The stacked inductor and transmission line are designed to match the impedance of notch filter and input impedance of buffers at the frequency around 20 GHz which maintain 20 GHz signals and attenuates 60 GHz LO feed-through and other spurious signals. The size of differential pair is chosen at Formula$2\times 10\ \mu{\hbox {m}}$ and the size of tail transistor is chosen as Formula$2\times 26\ \mu{\hbox {m}}$. As shown in Fig. 10, the simulated power conversion gain varies from −9.7 to −11.5 dB over the range of frequency from 58.32 to 64.8 GHz.

3) Notch Filter

Output signals of the mixer carry a 20 GHz output signal and undesirable signals caused by a strong LO input power. Thus, a passive LC band-rejection filter is implemented to attenuate the LO feed-through signal as shown in Fig. 11. The inductor used in this filter is custom-designed with an inductance of 92 pH and a quality factor of 9. The capacitor is chosen as 75 fF. The resultant attenuation of this notch filter is shown in Fig. 12. It shows an attenuation of about −20 dB at the frequency around 60 GHz to reduce the LO feed-through signal.

Figure 11
Fig. 11. Schematic of the notch filter, along with other building blocks.
Figure 12
Fig. 12. Simulated attenuation of the notch filter.

4) Transmission Line

Transmission line is mainly adopted for impedance match since it benefits from low loss. However, this method proves to be area intensive. As can be seen in [1], considerable chip area is occupied by matching blocks using a transmission line with a 10 Formula$\mu{\hbox {m}}$ signal line width. In order to reduce the chip area, a 6 Formula$\mu{\hbox {m}}$-width transmission is utilized for designing match blocks in this work [2]. Fig. 13 shows a top and cross-sectional view of the guided micro-strip line. It has a 6 Formula$\mu{\hbox {m}}$ signal-line width and a 7-Formula$\mu{\hbox {m}}$ gap between the signal and ground line. The distance between the side grounds is 20 Formula$\mu{\hbox {m}}$.

Figure 13
Fig. 13. Structure of the transmission line.
Figure 14
Fig. 14. Modeling results of (a) attenuation constant, (b) phase constant/frequency, (c) Q, and (d) characteristic impedance.

For an accurate device modeling, a careful de-embedding method has been carried out to remove the parasitics of the pad and interconnection. Fig. 14 shows the modeled and measured results including attenuation constant, phase constant, quality factor and characteristics impedance, of the transmission line adopted in this work. Measured and modeled results were calculated from S-parameter in measurement and HFSS simulation, respectively. A careful simulation for impedance matching between input and output ports of different blocks, e.g., RF and LO input ports and output port of mixer, has been carried out using an accurate transmission line model. The detailed length of transmission line of impedance matching is shown in Fig. 15.

5) Summary

Figure 15
Fig. 15. Full schematic of down-converting circuits, along with other building blocks.

The full down-conversion system is composed of three main blocks as discussed in details in the previous sub-chapters. The input impedance of the frequency doubler is designed to match the output impedance of PLL buffers through the use of transmission line and a stacked inductor. The single-ended output of the frequency doubler feeds to the RF port of the mixer. The matching between two ports is also done with the use of transmission line. The differential LO signals is input to one-stage buffers before input the LO ports of the mixer. The LO feed-through at the output of the mixer is filtered out by a notch filter. The output at frequency around 20 GHz is amplified by two-staged buffers. Then, it is divided to lower frequency by a divider chain and compare with the reference signal from the 20 GHz PLL.

The amplitude of output signals from the mixer carrying the 20 GHz output frequency is enhanced by two-stage buffers which are also designed using stacked inductors for gain peaking. From simulation, under a normal case of having 0 dBm input power from the 20 GHz PLL and −10 dBm input from the ILO, the output power over the range of frequency around 20 GHz is shown in Fig. 16. The output power varies from −1.7 to 0.14 dBm in the range of frequency from 19.44 to 21.6 GHz. The strongest spurious frequency is lower than −21 dBm at the frequency around 60 GHz. These output power levels are high enough to drive the next-stage dividers for digital calibration. Simulation results indicate that the calibration system introduces negligible phase noise degradation.

Figure 16
Fig. 16. Simulated output power of the down-conversion system.

D. Digital Calibration Circuit

The digital calibration circuit consists of a frequency-to-digital converter, and digital logics. In order to increase the frequency resolution, digital calibration circuits are triggered at 1/10 of the reference clock. Derivative frequency signals coming from the 60 GHz ILO and 20 GHz PLL are measured using digital counters, respectively. Outputs of the digital counters, in the form of binary numbers, are compared in the following logic circuit during each reference cycle for digital circuits. The output of logic circuit directly controls the code for DAC, giving rise to adjust the ILO free-running frequency. If the derivative frequency coming from the 60 GHz ILO is greater than that coming from the 20 GHz PLL, the output code of digital logic circuit is decremented to speed down the 60 GHz ILO free-running frequency. Similarity, if the derivative frequency coming from the 60 GHz ILO is less than that coming from the 20 GHz PLL, the output code of digital logic circuit is incremented to speed up the 60 GHz ILO free-running frequency. The flowchart of the above ILO frequency calibration procedure is summarized in Fig. 17, where Formula$N_{20\ {\rm GHz}\_{\rm PLL}}$ is the number of pulses of the divided frequency from 20 GHz PLL, Formula$N_{60\ {\rm GHz}\_{\rm ILO}}$ is the number of pulses of the down converted frequency from 60 GHz ILO, and Formula$N_{\rm error}$ is the difference in the number of pulses between down-converted signals from 20 GHz PLL and 60 GHz ILO.

Figure 17
Fig. 17. Flow chart of the ILO frequency calibration process.

A possible calibration algorithm is outlined as follows. It is noted that TDD system allows foreground calibration. Thus, the entire calibration procedure can be divided into initial and intermittent calibration. Initially, ILO free-running frequencies are measured in the foreground by down-converting system and all-digital calibration circuits, and digital DAC codes representing the information of each frequency band (e.g., 58.32 GHz, 61.56 GHz, etc.) can be stored in a memory. Thus, process variation can be calibrated during initial calibration. When millimeter-wave transceivers operate in TDD mode, the calibration system can monitor ILO free-running frequency drift mainly caused by temperature variation. In a short interval of time duration, the ILO free-running frequency shift is regarded as gradual and subtle changes. As a result, such a small frequency drift can be corrected easily within several calibration steps.

In order to demonstrate the feasibility of the proposed method, the initial and intermittent calibration is implemented in this design. However, the memory for the store and recall of the DAC and capacitor bank codes is not implemented in this design, and only one state can be recorded for the intermittent operation. The detail of calibration algorithm is shown in Fig. 18. After presenting the capacitor bank codes for coarse tuning, the calibration loop will calibrate the free-running frequency of the ILO for RX to the desired frequency and monitor the ILO free-running frequency drift at regular intervals afterwards. As a result, the proposed calibration system can always adjust the ILO free-running frequency as environment changes to be at the middle of the locking range at the target frequency band.

Figure 18
Fig. 18. DAC code and output frequency of ILO for RX against time.
Figure 19
Fig. 19. Chip microphotograph.
Figure 20
Fig. 20. Measured free-running frequency range of the ILO TEG.
Figure 21
Fig. 21. Measured locking range of the quadrature ILO at centered frequency of each channel.
Figure 22
Fig. 22. Measured spectrum at 20.16 GHz.
Figure 23
Fig. 23. Measured spectrum at 64.80 GHz.
Figure 24
Fig. 24. Measured phase noise at a carrier of 61.56 GHz.
Figure 25
Fig. 25. Measured phase noise performance across the entire frequency band.
Figure 26
Fig. 26. Measured 60 GHz output spectrum when (a) disabling the calibration and (b) enabling the calibration.
Figure 27
Fig. 27. Measured phase noise characteristics (a) from 10 samples, (b) as a function of power supply, and (c) over temperature, at a carrier frequency of 62.64 GHz.
SECTION IV

EXPERIMENTAL RESULTS

The proposed 60 GHz frequency synthesizer is implemented in a standard 65 nm CMOS process. The microphotograph of the fabricated synthesizer is shown in Fig. 19. The total chip area is 1.9 mm × 2 mm. PLL spectrum is measured with an Agilent E4448A PSA spectrum analyzer and a 50-to-75 GHz external mixer. The phase noise is evaluated using an Agilent E5052B SSA signal source analyzer and a 50-to-75 GHz external mixer.

In order to assist the evaluation of 60 GHz frequency synthesizer, a 60 GHz ILO TEG chip is also fabricated on the same die. As shown in Fig. 20, the measured ILO free-running frequency range is 58.3 GHz–65.4 GHz, and is covered with sufficient overlap between neighboring bands. The resulting frequency tuning range can cover all 60 GHz bands. Even though the free-running frequency of ILO in the complete frequency synthesizer is slightly dropped due to undesired parasitic capacitances, the measured tuning range of 58.1 GHz–65.0 GHz is still sufficient to cover all 60 GHz bands. As shown in Fig. 21, the measurement results indicate that the ILO has a locking range of about 180–380 MHz at 60 GHz bands, when the input power less than −2 dBm.

When the frequency of input reference clock is 24 MHz, the synthesizer can generate all 60 GHz channel bands (including channel bonding): 58.32 GHz, 59.4 GHz, 60.48 GHz, 61.56 GHz, 62.64 GHz, 63.72 GHz, and 64.8 GHz, which are defined by current 60 GHz wireless standards. The frequency synthesizer consumes 72 mW from a 1.2 V power supply. If the intermittent operation is disabled, the calibration circuits including down-converting circuits and digital circuits consume 65 mW additionally.

The measured phase noise characteristic of the 20 GHz PLL is less than −105.6 dBc/Hz at 1 MHz offset across the entire frequency channel. The measured phase noise characteristic of the 60 GHz frequency synthesizer is less than −95 dBc/Hz at 1 MHz offset across the entire frequency channel. The measured reference spur level varies from −52 dBc to −70 dBc. The output spectrum at 20.16 GHz is graphed in Fig. 22 displaying the typical locked spectrum for the 20 GHz PLL. The graph demonstrates that the 12 MHz reference spur are kept 65 dB below the carrier frequency, showing good matching between charge pump currents. The output spectrum at 64.80 GHz is illustrated in Fig. 23 indicating the typical locked spectrum for the 60 GHz frequency synthesizer. As shown in Fig. 24, the typical measured phase noise is −95.6 dBc/Hz at 1 MHz offset, from a carrier frequency of 61.56 GHz. Fig. 25 shows the measured phase noise across the entire frequency band. It is worthwhile to mention that the phase noise of the 20-GHz PLL is −107 dBc/Hz at 1 MHz offset at 20.52 GHz. Theoretically, the phase noise should become 9.54 dB higher at the 60 GHz ILO output. Noted that the calibration system introduces negligible noise, the 2-dB degradation at 1 MHz offset is caused by a limited locking bandwidth. Due to the absence of on-chip I/Q mixers, an I/Q imbalance of this millimeter-wave frequency synthesizer cannot be accurately measured since any connectors and cables can further introduce significant delays.

Table 1
TABLE I PERFORMANCE COMPARISON WITH OTHER STATE-OF-THE-ART 60 GHZ CMOS PLLS/VCOS1NORMALIZED TO 62.64 GHZ FROM 50.112 GHZ MEASUREMENT.

Fig. 26 shows the 60 GHz output spectra disabling and enabling the calibration. As can be seen, without carrying out calibration the ILO free-running frequency is far from the third harmonic of the 20.52 GHz injected signal, causing failure of injection-locking operation. When enabling the calibration, the ILO free-running frequency is corrected to vicinity of 61.56 GHz, thus guaranteeing the injection-locking operation. The DAC signals were not brought off-chip and could not be measured. It is noted that the output power indicated in Fig. 24 do not account for losses from cables and an external 50-to-75 GHz down-conversion mixer. The calibrated output power is −8 dBm. Fig. 27 shows the measured phase noise characteristic in various PVT conditions at a carrier frequency of 62.64 GHz, which shows that the proposed circuit can be successfully calibrated for any PVT conditions. Fig. 27(a) shows the measured phase noise from 10 different chips. Fig. 27(b) shows the effect of a variation of supply voltage on measured phase noise. Fig. 27(c) shows the effect of temperature variation from 0–100°C on the measured phase noise performance.

Table I compares the present 60 GHz frequency synthesizers/VCOs with the state-of-art publications [2], [5], [13], [14], [19], [20], [21]. This work could cover all 60 GHz channels and demonstrates a very good phase noise performance with quadrature output phase. To the best knowledge of authors', it is the first 60 GHz frequency synthesizer with frequency calibration for TDD transceivers.

SECTION V

CONCLUSION

A 60 GHz frequency synthesizer with frequency calibration scheme which can support IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, and ECMA-387 TX/RX front end is reported. A frequency calibration scheme is proposed to monitor the frequency drift caused by environmental variations. With carful design, the proposed synthesizer can be suited for millimeter-wave TDD transceivers.

ACKNOWLEDGMENT

The authors would like to acknowledge T. Yamaguchi and Y. Tsukui for their technical assistances.

Footnotes

This work was supported in part by MIC, SCOPE, MEXT, STARC, NEDO, Canon Foundation, in part by VDEC in collaboration with Cadence Design Systems, Inc., and in part by Agilent Technologies Japan, Ltd. This paper was approved by Guest Editors Antonio Liscidini and Doug Smith.

W. Deng, T. Siriburanon, K. Okada, and A. Matsuzawa are with the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo 152-8552, Japan (e-mail: deng@ssc.pe.titech.ac.jp).

A. Musa is with NTT Research Center, Atsugi, Kanagawa 243-0198, Japan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

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Authors

Wei Deng

Wei Deng

Wei Deng (S'08) received the B.S. and M.S. degrees in electronics engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2006 and 2009, respectively, and the Ph.D degree in electronics engineering from Tokyo Institute of Technology, Tokyo, Japan, in 2013.

His research interests include analog/RF/millimeter-wave transceiver systems and clock/frequency generation systems for wireline and wireless communications.

Dr. Deng was the recipient of the IEEE SSCS Travel Grant Award in 2010, the Honor Scholarship from 2010 to 2013, the Excellent Student Award at Tokyo Institute of Technology in 2011, the China Youth Science and Technology Innovation Award in 2011, the IEEE Solid-State Circuits Society Predoctoral Achievement Award in 2012, the Chinese Government Award for Outstanding Self-financed (non-government sponsored) Students Abroad in 2013, and the Tejima Research Award in 2013. He is a technical reviewer for several international journals and conferences.

Teerachot Siriburanon

Teerachot Siriburanon

Teerachot Siriburanon (S'10) received the B.E. degree in telecommunications from Sirindhorn International Institute of Technology (SIIT), Thammasat University, Thailand and the M.E. degree in physical electronics from Tokyo Institute of Technology, Tokyo, Japan, in 2010 and 2012, respectively. He is currently pursuing the Ph.D. degree in Physical Electronics at Tokyo Institute of Technology, Japan.

His research interests are CMOS RF/millimeter-wave transceiver systems and clock/frequency generations for wireless and wireline communications.

Ahmed Musa

Ahmed Musa

Ahmed Musa (S'11) received the B.Sc. degrees in electrical engineering and computer engineering from King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, KSA, in 2006, and the M.S. and Ph.D. degrees in physical electronics from Tokyo Institute of Technology, Tokyo, Japan, in 2009 and 2013, respectively.

He is currently working with NTT Research Center, Atsugi, Japan. His research interests include CMOS RF/microwave circuit design, low power design, and all digital PLL frequency synthesizers.

Dr. Musa received the ASP-DAC Special Feature Award in 2011 and the IEEE SSCS Predoctoral Achievement Award for 2012–2013.

Kenichi Okada

Kenichi Okada

Kenichi Okada (S'99–M'03) received the B.E., M.E. and Ph.D. degrees in Communications and Computer Engineering from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively.

From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. From 2003 to 2007, he worked as an Assistant Professor at Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama, Japan. Since 2007, he has been an Associate Professor at Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan. He has authored or co-authored more than 200 journal and conference papers. His current research interests include reconfigurable RF CMOS circuits for cognitive radios, 60 GHz CMOS RF front-ends, and low-voltage RF circuits.

Dr. Okada is a member of IEEE, the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and the Japan Society of Applied Physics (JSAP). He is a member of the ISSCC Technical Program Committee. He received the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006, the ASP-DAC Special Feature Award in 2011, and 32 international and domestic awards.

Akira Matsuzawa

Akira Matsuzawa

Akira Matsuzawa (M'88–SM'01–F'02) received B.S., M.S., and Ph. D. degrees in electronics engineering from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997 respectively.

In 1978, he joined Matsushita Electric Industrial Co. Ltd. Since then, he has been working on research and development of analog and Mixed Signal LSI technologies; ultrahigh speed ADCs, intelligent CMOS sensors, RF CMOS circuits, digital read-channel technologies for DVD systems, ultrahigh speed interface tech-nologie s for metal and optical fibers, a boundary scan technology, and CAD technology. He was also responsible for the development of low power LSI technology, ASIC libraries, analog CMOS devices, SOI devices. From 1997 to 2003, he was a general manager in advanced LSI technology development center. On April 2003, he joined Tokyo Institute of Technology and he is a professor on physical electronics. Currently he is researching in mixed signal technologies; CMOS wireless transceiver, RF CMOS circuit design, data converters, and organic EL drivers.

Dr. Matsuzawa served the Guest Editor in chief for special issue on analog LSI technology of IEICE Transactions on Electronics in 1992, 1997, and 2003, the vice-program chairman for International Conference on Solid State Devices and Materials (SSDM) in 1999 and 2000, the Co-Chairman for Low Power Electronics Workshop in 1995, a member of program committee for analog technology in ISSCC and the guest editor for special issues of IEEE Transactions on Electron Devices. He has published 26 technical journal papers and 46 international conference papers. He is coauthor of 8 books. He holds 34 registered Japan patents and 65 US and EPC patents. In April 2003 he joined, as a Professor, the Department of Physical electronics at Tokyo Institute of Technology. He received the IR100 award in 1983, the RD100 award and the remarkable invention award in 1994, and the ISSCC evening panel award in 2003 and 2005. He is an IEICE Fellow since 2010.

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