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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

Figure 1

Figure 1
Architecture of Mb/C SAR ADC.

Figure 2

Figure 2
Passive sampling front-end circuit.

Figure 3

Figure 3
R-C model of the DAC settling path.

Figure 4

Figure 4
Proposed ADC architecture and timing diagram.

Figure 5

Figure 5
Implementation of the interpolated sampling front-ends with cross-coupled bootstrapping network.

Figure 6

Figure 6
(a) Conventional and (b) proposed interpolated sampling circuits topology in 2-b/cycle SAR structure.

Figure 7

Figure 7
Switching operation of the reference DAC.

Figure 8

Figure 8
Different implementations of the decoder unit in the third conversion cycle by (a) and/nand gates and (b) cascaded inverters.

Figure 9

Figure 9
Implementation of comparator offset calibration.

Figure 10

Figure 10
Circuit implementation of dynamic comparator.

Figure 11

Figure 11
Layout implementation of DAC unit cell.

Figure 12

Figure 13

Figure 13
Measured DNL and INL (a) without and (b) with comparator offset calibration at 400 MS/s.

Figure 14

Figure 14
Measured dynamic performance. (a) FFT spectrum at 2-MHz input (output decimated by 25). (b) FFT spectrum at Nyquist input (output decimated by 25). (c) SNDR versus conversion rate. (d) SNDR versus input frequency.