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Science and Engineering Beyond Moore's Law

Figure 1

Figure 1
The number of transistors per microprocessor chip versus time, showing introduction of new enabling technologies.

Figure 2

Figure 2
Benchmark capability Formula$\mu$ (instructions per second) as a function of Formula$\beta$ (bits per second).

Figure 3

Figure 3
Transistor cost as a function of the cumulative number of transistors shipped [12].

Figure 4

Figure 4
Personal computer cost (inflation adjusted) per millions of instructions per second versus cumulative units shipped [12].

Figure 5

Figure 5
Semiconductor FET: (a) materials system; (b) generic floorplan; (c) scaling limits; and (d) connected binary switches.

Figure 6

Figure 6
The two-energy-barrier model for a memory cell: (a) the principle of storage and sensing; (b) write operation; and (c) read operation.

Figure 7

Figure 7
Representation for maximum device density for (a) logic and (b) memory circuits.

Figure 8

Figure 8
Illustration of the integration of many technologies on a single CMOS substrate [35].

Figure 9

Figure 9
State variable and different facets of information processing system.

Figure 10

Figure 10
ITRS taxonomy for information processing nanotechnologies [22].

Figure 11

Figure 11
Unicellular organism as information processor.

Figure 12

Figure 12
Protein molecule formed from different amino acids (shown as circles of different colors).

Figure 13

Figure 13
A fragment of DNA molecule formed from four different nucleotides.

Figure 14

Figure 14
Comparison of significant parameters of the bio-Formula$\mu$cell and the Si-Formula$\mu$cell.