Dynamic-range enhancement of an optimized 1-bit A/D converter

A technique is demonstrated for extending the dynamic range of 1-bit analog-to-digital converters (ADCs) that sample at the maximum rate using a sinusoid reference r(t)=A/sub r/ cos(2/spl pi/f/sub r/t). The ADC has a detection limit B=/spl pi/A/sub r//spl delta///spl utri/, where 2/spl delta//sub s/ is the base-clock period, and /spl utri/=sampling interval=1/2f/sub r//spl ges/2/spl delta/. Optimal sampling is achieved at /spl utri/=2/spl delta/, but with large quantization errors found in the sampled representation of the input signal s(t). Dithering with noise n/sub /spl sigma//(t) of appropriate variance /spl sigma//sup 2/ is utilized to measure a subthreshold s(t) where |s(t)|