Low thermal-budget ultrathin NH/sub 3/-annealed atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics with excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics annealed in NH/sub 3/ at a moderate temperature of 550/spl deg/C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO/sub 2/ stack dielectrics without NH/sub 3/-annealing and conventional thermal SiO/sub 2/ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices.