Characterization of two standard CMOS EEPROM designs

The objective of this project is to characterize the programming speed and the programming voltage requirements of floating gate EEPROM cells made in a generic CMOS process (e.g. a MOSIS tiny chip - AMI C5N 0.5 micron technology). The charge trapping and injection is based on carrier injection using cold tunneling (Fowler-Nordheim effect). The variable constraints are the sizes of the injector capacitors and control gate capacitors. All necessary positive voltages will be generated using a charge pump requiring a single power supply.