A low-power cache design for CalmRISC/sup TM/-based systems

Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dominant chip area in microprocessors, and it becomes increasingly important to design power-efficient cache memories. This paper describes an experimental low-power on-chip cache system designed for a 32-bit processor core called CalmRISC/sup TM-/32. A number of architectural optimizations were applied to the instruction and data caches, which significantly decrease the number of tag and data memory accesses and the amount of memory traffic to and from off-chip memory. Implemented in a 0.18 /spl mu/m CMOS technology, the presented instruction and data caches consume 90 /spl mu/A/MHz and 72 /spl mu/A/MHz at 1.8 V, respectively.