Solder joint fatigue and reliability of chip scale packages: a failure analysis strategy

This paper outlines an optimal approach for board level chip scale package (CSP) failure analysis, where the chip and printed circuit board (PCB) are analyzed as a single unit. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was specifically developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions on both package and PCB, substrate warpage, heating profiles/reflow, intermetallic compound (IMC) thickness and solder joint voids.