Low-complexity bit-parallel systolic architecture for computing AB/sup 2/+C in a class of finite field GF(2/sup m/)

An algorithm for computing AB/sup 2/+C over a finite field GF(2/sup m/) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems.