An approach to mapping the timing behavior of VLSI circuits on emulators

The time spent in simulation grows in an exponential form with the complexity of the circuit. Therefore, improving the simulation speed can represent a significant profit regarding the verification time. Several approaches can be used to speedup the simulation. These recent years, FPGAs have been used to develop emulators. These systems are composed of several thousands of FPGAs connected together through a programmable network. Although this approach seems very attractive with regard to the speedup, all the information included in a circuit description cannot be mapped on the emulator. In this paper, we propose a method to reproduce the timing behavior of the circuit on an emulator.