New queuing strategy for large scale ATM switches

We study the different buffering techniques used in the literature to solve the contention problem in ATM switching architectures. The objective of our study is to determine the buffer requirements needed to achieve a given quality of service (e.g., a given cell loss probability). Based on this study, we propose a combined central and output queuing (CCOQ) technique to be used in designing large-scale ATM switches. Also, we propose a general design technique for an N/spl times/N large-scale ATM switch with a suitable CCOQ buffer size to reduce both the cell loss probability and the complexity of the memory modules. The switch has to be designed such that it can be implemented using the smallest number of VLSI chips possible. It should be also reliable for commercial use. The switch should support multicast and priority control functions.