A programmable focal-plane MIMD image processor chip

An 80/spl times/78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11/spl times/11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm/sup 2/ in a 1.2-/spl mu/m CMOS process. The application of the chip to line-segment orientation detection is also presented.