Mitigation of Inter-Cell Interference in Flash Memory With Capacity-Approaching Variable-Length Constrained Sequence Codes

We propose using variable-length constrained sequence codes to mitigate inter-cell interference (ICI) in all-bit-line flash memory with multi-page programming for single-level cell, multi-level cell, and triple-level cell flash memory structures. We outline constraints that mitigate ICI in these systems based on an observation of the Gray mapping of data symbols, and we derive the capacity of each constraint. Based on a finite state machine representation of each constraint, we construct variable-length constrained sequence codes with code rates very close to capacity to mitigate ICI in these flash memories. We then exploit the inherent error control capability of the proposed constrained sequence codes to alleviate error propagation. Finally, we integrate these codes with error control codes and present simulation results that demonstrate the enhanced bit error rate performance that can be achieved.