Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the I
_D
-V
_G
distribution at various V
_DS
values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full I
_D
-V
_G
distribution rather than just V
_T
distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current (I
_READ
) to show excellent accuracy. The method also shows a 30× improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method.