7-Bit SiGe-BiCMOS Step Attenuator for X-Band Phased-Array RADAR Applications

This letter presents a 7-bit CMOS step attenuator for the first time in the literature, designed with isolated NMOS (iNMOS) using IHP 0.25 μm SiGe BiCMOS process technology. INMOS' are utilized to decrease the insertion loss (IL) caused by internal parasitic capacitances, which is especially important when cascading 7 attenuation stages. The attenuator has a measured maximum relative attenuation of 16.51 dB with an increment of 0.13 dB while exhibiting a root mean square (RMS) amplitude error of less than 0.13 dB, the lowest error ever reported. In addition, the attenuator exhibits an RMS phase error of 2.7° at 10 GHz. The measured input referred 1 dB compression point (IP
_{1 dB}
) of the attenuator is 12.5 dBm at 10 GHz. Moreover, the attenuator demonstrates an IL of less than 12.5 dB in X-band (8-12 GHz). The total chip area excluding pads is 0.29 mm
²
.