Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories

On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the standard global corner of memories in any chip. It leverages a current-mirror and a near-threshold biased bitcell array structure that changes the output voltage of the circuit in accordance with changes in the process corner. BPMON separately tracks bitcell NMOS and bitcell PMOS process corners. Silicon data from over 100 chips from five wafers in 28 nm CMOS shows correct bitcell process corner predictions. These predictions show the expected strong correlation with read and write vccmin, enabling vccmin to be lowered below specifications while still achieving a 100% yield.