ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18-μm, 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n
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region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p
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region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p
⁺
region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater.