A 10-b 200-kS/s 250-nA Self-Clocked Coarse–Fine SAR ADC

A 10-b ultralow-power successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 0.18- μm CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low-resolution comparators in the coarse converter enables compensating for the offset mismatches between the coarse and fine ADCs. The comparator of the fine SAR ADC obtains high sensitivity and very low power owing to a gain-enhanced dynamic preamplifier. A loop delay line generates all the phases for the SAR logic and permits three different modes of operation: on-demand, self-clocked, and clocked. In the clocked mode and at 200 kS/s, this converter achieves a 9.05-b effective number of bits (ENOB) while consuming 200 nW. The resulting figure of merit (FoM) is 1.88 fJ/conversion-level.