Hot-Carrier Instability of nMOSFETs Under Pseudorandom Bit Sequence Stress

Hot-carrier instability under stress conditions emulating a random logic operation (random ON and OFF) has been investigated using pseudorandom bit sequence (PRBS) stress patterns. Furthermore, the impacts of PRBS stress on circuit-level operation have been compared with the conventional dc (static) and ac (periodic) stress conditions using hot-carrier-induced random timing jitter. It was observed that the recovery achieved by charge trapping and detrapping under dynamic stress conditions significantly affects the degree of hot-carrier degradation.