Implementation of a Near-Optimal Detector for Spatial Modulation MIMO Systems

This brief presents a hardware implementation of a detector for spatial modulation multiple-input multiple-output (SM-MIMO) communication systems. The proposed detector employs the signal-vector-based list detection method, but the original method is modified to realize a low-complexity implementation. In addition, the proposed detector is designed based on the dual-data-path architecture, in which antenna selection and symbol detection are separately performed with different precision levels to reduce the hardware complexity while achieving a near-optimal error-rate performance. The proposed detector is implemented with 87.4-K logic gates in a 0.18-μm CMOS technology, and its throughput is 858 Mb/s for 8 × 4 64 quadrature amplitude modulation SM-MIMO systems, where the operating frequency is 286 MHz, and the power consumption is 121.3 mW. This manifests that the proposed detector is very efficient with respect to the gate count as well as the energy consumption.