Compact Modeling of Negative $V_{t}$ Shift Disturb in NAND Flash Memories

The negative V
_t
shift disturb is one of the new scaling limiters for the NAND Flash technology, since it severely affects the reliability of ultra-scaled products, lowering the read margin between the distributions in multilevel cell architectures. However, even if the phenomenon was thoroughly investigated, it lacks a proper model to be exploited for the development of tailored management solutions. In this paper, we have developed a compact model for the negative V
_t
shift disturb simulation in NAND Flash arrays. The model accurately reproduces experimental data retrieved on a 26-nm technology. The application of the model for the fast and accurate statistical assessments of the reliability loss induced by the disturb is shown through the execution of Monte Carlo simulations.