A 200-MS/s Phase-Detector-Based Comparator With 400-$\mu\text{V}_{\mathrm{rms}}$ Noise

A low-noise phase-detector-based comparator is proposed for SAR ADCs. It can reduce the thermal-induced noise as well as the probability of the metastability. The proposed comparator is composed of two front-end dynamic comparators and a backend phase detector. The comparator has been fabricated in a 0.18-μm CMOS technology and achieves 400-μVrms noise at a conversion rate of 200 MHz under a 1.8-V supply voltage while consuming 78 μW. Its active area is 0.001 mm
²
.