Design of a Digital Address-Event Triggered Compressive Acquisition Image Sensor

This paper describes a compressive acquisition image sensor realizing an on-chip focal plane compressive sensing algorithm. The proposed design enables signal sampling at a rate much lower than the Nyquist rate while preserving the capability to recover the useful information of the signal. Address events are employed to convert illumination intensity into time domain information, eliminating the use of analog-to-digital converters and effectively reducing the readout rate. A pixel-level all digital address event triggered compressive sensing request generator is implemented. An image pixel array of 48 × 72 was fabricated in 0.18 μm standard CMOS technology, featuring a 22-transistor all-digital pixel architecture with a size of 15 × 15 μm
²
and a fill factor of 32.4%. Experimental results show a higher than 10 compression ratio with a power consumption of 1.56 mW at 23 fps under image acquisition mode.