Revolutionizing validation: The Intel approach for TTM

Summary form only given. Intel is focused on gaining a foothold in the burgeoning mobile/IOT computing market. One of the unique challenges in this dynamic market is the aggressive time-to-market (TTM) requirement. In the past, the length of the silicon validation stage for Intel SoCs contributed to the company's inability to deliver products on time, taking up to two years for prior projects. To address this situation, the Devices System Validation group set a transformation goal to reduce time from first silicon to PRQ for base and derivative products. While a validation execution strategy can be optimized based on perceived risk in changes to HW, FW, and SW, accounting for silicon debug is far more difficult. It is nearly impossible to predict the amount of time necessary to debug the breadth and quantity of issues (Sightings) that will be found during execution. The number of sightings generated over the course of a project depends on many factors, including the health of the RTL and process, the stability of the FW and SW code base, and the technical strength of the execution team. This unpredictability results in many challenges when attempting to hit a target time window from first silicon to Production Ready Quality (PRQ). Moorefield, a platform based on Intel's 22 nm Atom-based SoC named Anniedale, was the first project to achieve a goal of first silicon to Production in two quarters. A major factor in this achievement was the strategy employed by the team to manage the risk in silicon validation and debug with aggressive shift left effort that included early and close collaboration with the customer, platform, and design teams. This strategy is built on several key pillars. 1) Comprehensive Design for Debug (DFD) features and tools that are fully validation in pre-silicon & emulation to prepare for critical debug scenarios at customer platforms. 2) Early and close engagement with the lead customer and platform teams to develop an alpha level quality SW in emulation. 3) Employing requirements-based validation to focus on validating only the form factor OS application use-cases. 4) A strict platform regressions strategy that can be scaled from pre to post silicon 5) Centralized System Debug organization to accelerate time to closure of critical sightings. In this talk we will be detailing and presenting the innovative strategies the System Validation (SV) organization took around the these pillars to achieve a successful launch of the Moorefield-based Asus tablet and phone in record breaking time.