Application-Specific Low-Power Multipliers

In this paper we propose techniques for decreasing the power consumption of multipliers. The proposed techniques exploit data statistics. Specifically we propose two architectures for two-input signed multipliers, namely selective activation multiplier and partitioned multiplier. To illustrate the benefits achieved by the proposed architectures, their application in the implementation of multipliers used in DCT and DWT is detailed. The power reduction reported is up to
$20.7$
percent for cases of practical interest. The proposed multipliers can be easily implemented, adapted, and combined with prior-art low-power techniques with a moderate area and time overhead.