Magnonic holographic co-processor: An approach to energy-efficient complementary logic circuitry

Power consumption has emerged as the major problem limiting the scalability and the functional throughput of modern logic devices [1]. This problem has stimulated a great deal of interest to research alternative technologies, which may overcome the constraints inherent to complementary metal-oxide-semiconductor (CMOS)-based circuitry and provide a route to more functional and less power-consuming logic devices. Spintronics is one of the possible directions [2]. The utilization of spin opened a new horizon for the development of non-volatile memory and logic elements. It also offers novel approaches to data transfer. The integration of the spin-based components will require new architecture solutions. In this work, we discuss the possibility of building Magnonic Holographic Co-Processor (MHcP) aimed to complement CMOS in special task data processing. The main advantage of MHcP is combination of memory and logic in one unit. This idea is illustrated in Figure 1. On the left side, it is shown the Von Neumann architecture scheme. It consists of Memory, Control Unit and Arithmetic Logic Unit. The separation between the memory and the logic units is an attribute of the traditional architecture. On the right side of Figure 1, there are shown the schematics of MHcP, where the large portion of memory is embedded into the magnonic holographic logic unit. This architecture solution allows significantly minimize power consumption required for memory addressing and information transfer between the units. The advantage is most prominent in special task data processing requiring large amount of memory resources (e.g. database search).