Hybrid iSLIP scheduling algorithm for Network on Chip

Network on Chip is a set of hardware component that communicates together. The communication system must achieve maximum throughput while maintaining the system correctness, stability and eliminating starvation. The ideal solution among existing NoC architecture is the Switch Fabric. As it is known, the scheduler is the Switch Fabric brain. Moreover, the scheduling algorithm choice must be suitable to the application requirement. By nature, NoC architecture is composed of two types of core that are master cores and slave ones, called also processor and coprocessor. Trying to give the suitable solution for such hardware architecture, we propose our own scheduling algorithm called Hybrid iSLIP which is a kind of prioritized iSLIP. This paper presents a modeling, design and an evaluation of a hardware scheduler for High-Speed Virtual output Queuing using the Hybrid iSLIP algorithm. A comparison is done between the iSLIP algorithm and the Hybrid one by determining the complexity and the convergence order for both them.