Memory BIST for on-chip monitoring of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array

We present a Built-in Self Test (BIST) methodology for on-chip failure analysis of via/contact voiding due to electromigration (EM) and stress-induced voiding (SIV) in SRAM cells. Our BIST system aims to detect wearout in faulty cells and identify the location of the failure in the cell. This enables more efficient physical failure analysis.