Feasibility analysis of high-density STTRAM designs with crossbar or shared transistor structures

Spin-transfer-torque RAM (STTRAM) is considered one of the most promising nonvolatile memories (NVMs) for embedded applications, owing to its long endurance and fast speed. A STTRAM cell is usually formed by connecting a MTJ (magnetic tunnel junction) with an access transistor (i.e., 1T-1MTJ). Due to high current required to switch the MTJ, the access transistor has to be sufficiently wide and is often much larger than the MTJ itself. Consequently, STTRAM bit size is dominated by the transistor size and may even exceed 50F
²
(F: feature size of a technology node) [1]. Improving bit density may reduce cost and enable new applications, e.g., storage-class-memory (SCM). Multi-level-cell (MLC) through device engineering has been proposed for STTRAM; however more significant density increase may be achieved by modifying memory access structures: a crossbar array (CBA) design (Fig. 1) or a shared access transistor design (Fig. 2) [1, 2]. In both designs, sneak paths present the most important challenge. This paper analyzes the feasibility of the two high-density designs based on a nonlinear CBA model and proposes an improved design with two-terminal (2T) nonlinear selectors connected to MTJs to suppress sneak leakage [3].