Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent $V_{\rm TH}$ Variability

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V
_TH
shifts and fluctuations, which are even visible during the I
_D
-V
_G
tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times τ
_c
and τ
_e
, and their impact on V
_TH
as a function of gate voltage V
_G
and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V
_G
swing and operational temperatures.