Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a lightshield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).