Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time

This letter reports on the spike anneal temperature influence on the retention time of 1T-dynamic random access memory cells using a single silicon-on-insulator transistor on ultrathin buried oxide wafers. A 20 °C temperature difference (from 1070 °C to 1050 °C) in the peak process temperature during the spike anneal after the source/drain implantation caused an order of magnitude increment in the retention time. The lower temperature analyzed (1050 °C) increases the retention time up to 100 ms because of the lower drain electrical field and tunneling current.