Realization of a low power sensor node processor for Wireless Sensor Network and its VLSI implementation

In a large Wireless Sensor Network, power efficiency of sensor node is one of the most important factor. Nowadays, WSN based solution have been used widely and is getting pervasively deployed in various applications. Long time operating capability with efficient energy management plays very important role for a sensor node. In this article, the sensor intelligence has been emerged with a low power processor model. Sensor node within a single chip has been developed and implemented on a high performance FPGA kit. Xilinx ISE 14.3 simulator has been used to design the processor model in VHDL code. An efficient sleep scheduling with a synchronized timer and algorithm to achieve optimum power efficiency has been adopted in this design. Realization up to RTL schematic level has been performed and results power efficiency of almost 90% compared to commercially available microcontroller based sensor.