A Simple Method to Grow Thermal ${\rm SiO}_{2}$ Interlayer for High-Performance SPC Poly-Si TFTs Using ${\rm Al}_{2}{\rm O}_{3}$ Gate Dielectric

A simple method is proposed to grow thermal SiO
₂
interlayer when performing solid-phase-crystallized (SPC) process. By employing such interlayer between SPC polycrystalline silicon channel and Al
₂
O
₃
gate dielectric, highperformance SPC thin-film transistors (TFTs) with field effect mobility of 67.80 cm
²
V s
^-1
and ON/OFF ratio of 2.31 × 10
⁸
at V
_ds
= -0.1 V are achieved due to the superior interface quality and improved grain boundaries by the incorporation of excess Si interstitials. The TFT with interlayer also exhibits good reliability under negative bias temperature stress test.