A 3.6-to-1.8-V Cascode Buck Converter With a Stacked $LC$ Filter in 65-nm CMOS

This brief presents the analysis, design, and measurements of an integrated synchronous cascode dc-dc buck converter in 65-nm CMOS. Guidelines for optimal design of each thick-oxide device in the switch bridge are derived in order to obtain enhanced power efficiency. The form factor is improved by stacking the high-Q inductor and other converter components. The circuit shows a measured efficiency of 67.9% when converting 3.6 to 1.8 V at a switching frequency of 120 MHz and a load current of 140 mA. The efficiency enhancement factor of +26.4% is among the highest for integrated buck converters.