Design development & performance analysis of high speed comparator for reconfigurable ΣΔ ADC with 180 nm TSMC technology

Comparator design has a crucial influence on the overall performance that can be achieved by Analog to Digital Converter (ADC). The need for programmable analog parts is in research from several years. The ADC's being mixed signal in nature requires novel architectures to achieve programmability by digital means. The work being carried out aims to bring out architecture of differential pin, which can give better performance when configured as comparator for reconfigurable Sigma Delta ΣΔ ADC, which fulfil an important role in today's mostly digital mixed-mode systems as interface circuits between the analog world and the powerful digital signal processing. This comparator for a ΣΔ ADC is designed using CMOS 180nm TSMC technology. The simulation is carried out with h-SPICE tool and results prove the circuit operates maximum up to 400 MHz clock speed with gain of 110K. The layout simulation results running up to 250MHz with a gain of 74K agree with the parasitic overhead.