NMOS/PMOS resistance calibration method using reference frequency

A method of NMOS and PMOS transistor resistance variation detection and compensation, using reference clock frequency is presented. The proposed method provides opportunity to measure and compensate MOS device resistance deviation, due to technology process, voltage and temperature variations, separately. Detection of variations is realized using the proposed digital logic block. Efficiency of the suggested method is tested and presented for a high-speed voltage controlled oscillator.